--- title: "Dual slope ADC; why quad slope is more accurate" subject: "Advanced Electronics" chapter: 3 key: "semester_4/advanced_electronics:dual-slope-quad-slope" source: https://www.bctengineer.com/q/semester_4/advanced_electronics/dual-slope-quad-slope site: BCT Engineering --- # Dual slope ADC; why quad slope is more accurate Advanced Electronics · Chapter 3: Digital-to-Analog and Analog-to-Digital Conversion - Asked in: 2069 Chaitra, 5+2 marks - Video: [Dual Slope or Integrating type ADC](https://www.youtube.com/watch?v=K07T1dSnwxY) — TutorialsPoint - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_4/advanced_electronics/dual-slope-quad-slope - Whole chapter: https://www.bctengineer.com/md/semester_4/advanced_electronics/chapter-3 ## Question Explain the working principle of dual slope integrating type ADC with necessary diagrams. Why is the output of quad slope ADC more accurate than that of dual slope ADC? ## Short answer Dual-slope ADC integrates Vin for fixed time T1, then de-integrates using −Vref until zero crossing; T2 ∝ Vin, cancelling R,C,clock drift. Quad-slope adds an auto-zero cycle that measures and subtracts offset errors, improving accuracy especially for small inputs. ## Answer A dual slope integrating ADC integrates the input for a fixed time T1, then integrates a reference of opposite polarity until the output returns to zero. The time T2 taken for this is measured by a counter and is proportional to the input. #### Block diagram ```text Vin --o S1 C -Vref--o--+--[R]--+--------||--------+ | | (-)\ | >---------------+--Vo1-->[COMPARATOR] (+)/ | | v GND CLOCK-->[COUNTER]<-->[CONTROL] | digital out ``` #### Working 1. **Reset:** the counter is cleared and the integrator capacitor is shorted. 2. **Run-up (T1 fixed):** S1 connects Vin. The integrator output becomes Vo1 = −Vin·T1/RC. T1 = 2ⁿ clock pulses, and the counter overflows at the end of T1. 3. **Run-down (T2 variable):** S1 connects −Vref. The output returns to zero at a fixed slope Vref/RC while the counter counts from zero. 4. **End:** the comparator detects zero crossing and stops the counter. ```text Vin·T1/RC = Vref·T2/RC N2 = N1 · Vin/Vref ``` ```text Vo1 | /\ <- high Vin | / \ | / /\ \ <- low Vin (same down slope) |__/_/__\_\_____ t |<-T1->|T2a| |<-T2b->| ``` R, C and clock drift cancel out, and noise (including mains hum) is averaged out. It is accurate but slow, and it is used in DMMs. #### Why quad slope is more accurate than dual slope A dual slope ADC still has errors that do not cancel: integrator op-amp offset voltage, input bias current, comparator offset and delay, and switch leakage. These add a fixed error, especially near zero input. A quad slope ADC adds a **calibration (auto-zero) cycle**: - **Slopes 1 and 2:** the input is grounded (Vin = 0). The converter integrates and de-integrates, and the count obtained measures only the offset errors. - **Slopes 3 and 4:** the normal dual slope conversion of Vin, which includes the same errors. - The control logic subtracts the first count from the second, so the offset and bias errors cancel. The result depends only on Vin/Vref, so the quad slope ADC gives better accuracy, especially for small inputs, at the cost of a longer conversion time. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What happens during the fixed time T1 of a dual slope ADC? A. The reference is integrated until zero B. The input Vin is integrated for a fixed time T1 (2^n clock pulses) C. The counter is reset and the capacitor is shorted D. The comparator is disabled and the input is grounded Answer: B. In run-up the integrator integrates Vin for fixed T1, giving Vo1 = -Vin T1/RC. (Key point: Run-up phase) 2. What relation gives the digital count in a dual slope ADC? A. N2 = N1 x Vref/Vin B. N2 = N1 x Vin/Vref C. N2 = N1 + Vin/Vref D. N2 = Vin x Vref Answer: B. Equating Vin T1/RC = Vref T2/RC gives N2 = N1 Vin/Vref. (Key point: Conversion result) 3. Why do R, C and clock drift not affect the dual slope result? A. They appear in both the run-up and run-down equations and cancel B. They are trimmed by laser C. The comparator corrects them D. The counter ignores them Answer: A. Both slopes depend on RC and the same clock, so these terms cancel in the ratio. (Key point: Why R, C and clock do not matter) 4. Why is a quad slope ADC more accurate than a dual slope ADC? A. It uses a faster clock B. It uses a larger capacitor C. A calibration cycle with Vin = 0 measures the offset and bias errors, which are subtracted from the conversion D. It uses 4 comparators Answer: C. Slopes 1 and 2 with grounded input measure the offset errors; subtracting that count cancels them. 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