---
title: "Mirror error and active-load differential gain"
subject: "Advanced Electronics"
chapter: 1
key: "semester_4/advanced_electronics:mirror-error-active-load-gain"
source: https://www.bctengineer.com/q/semester_4/advanced_electronics/mirror-error-active-load-gain
site: BCT Engineering
---

# Mirror error and active-load differential gain

Advanced Electronics · Chapter 1: Operational Amplifier Circuits

- Asked in: 2069 Chaitra, 2+5 marks
- Video: [lecture 34 MOSFET differential amplifier with active load](https://www.youtube.com/watch?v=GJ_20tqNYzA) — Sumita Gupta
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_4/advanced_electronics/mirror-error-active-load-gain
- Whole chapter: https://www.bctengineer.com/md/semester_4/advanced_electronics/chapter-1

## Question

What are the reasons for the output current of a simple current mirror not being exactly equal to the reference current? Show that the voltage gain of a differential amplifier with active load is doubled compared to that with passive load (RC).

## Short answer

Reasons: finite β (IO=IREF/(1+2/β)), Early effect, mismatch. With passive RC loads, single-ended differential gain is gm·RC/2. An active current-mirror load steers both signal currents to the output, yielding gain gm·(ro2‖ro4), which is double for equal load resistance.

## Answer

#### Reasons IO ≠ IREF in a simple current mirror
In a simple two-transistor mirror the output current IO is not exactly IREF because:

1. **Finite β (base current):** IREF must supply IC1 plus both base currents:
   IREF = IC + 2IC/β, so **IO = IREF/(1 + 2/β)**. For β = 100, IO is about 2% less than IREF.
2. **Early effect (finite ro):** VCE1 = VBE ≈ 0.7 V but VCE2 is set by the load and is usually larger. Because of base-width modulation, IO = IC1(1 + (VCE2 − VBE)/VA), so IO is slightly larger and changes with output voltage.
3. **Mismatch:** small differences in IS (emitter area, doping) and temperature between Q1 and Q2 make VBE1 = VBE2 give unequal currents.

#### Gain of differential amplifier: active load vs passive load
Consider a BJT differential pair Q1–Q2 with tail current I, gm = (I/2)/VT. A differential input vd = v1 − v2 gives each transistor ±vd/2, so

```text
ic1 = +gm·vd/2 ,   ic2 = -gm·vd/2
```

**Passive load (RC in each collector), single-ended output at Q2:**

```text
vo = -ic2·RC = gm·RC·vd/2
Ad(passive) = gm·RC/2
```

The signal current of Q1 is lost in its own RC.

**Active load (PNP current mirror Q3–Q4):**

```text
      +VCC ---- Q3(diode) ==== Q4 ---- +VCC
                  |             |
                  | ic1         +----- vo
                  |             |
       v1 ---B   Q1            Q2   B--- v2
                  +------+------+
                         I
                       -VEE
```

Q3 carries ic1, and the mirror copies it into Q4, so Q4 pushes ic1 = +gm vd/2 into the output node while Q2 draws ic2 = −gm vd/2 from it:

```text
io = ic1 - ic2 = gm·vd/2 + gm·vd/2 = gm·vd
vo = gm·vd·(ro2 ‖ ro4)
Ad(active) = gm·(ro2 ‖ ro4)
```

For the same load resistance R (ro2‖ro4 = RC = R):

```text
Ad(active)/Ad(passive) = gm·R / (gm·R/2) = 2
```

So the active load **doubles** the gain, because both halves of the signal current reach the output. Since ro2‖ro4 is also much larger than a practical RC, the real gain is many times higher.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. For β = 100, how does IO compare with IREF in a simple mirror?
   A. Exactly equal
   B. About 2% less
   C. About 2% more
   D. About 50% less
   Answer: B. IO = IREF/(1 + 2/β) = IREF/1.02, about 2% less. (Key point: Finite β)

2. Why is the passive-load single-ended gain only gm RC/2?
   A. The signal current of Q1 is lost in its own RC
   B. RC is halved
   C. gm is halved
   D. Q2 is off
   Answer: A. Only Q2's current gm vd/2 reaches the output through RC. (Key point: Passive gain)

3. What is the single-ended gain with the PNP mirror load?
   A. gm/(ro2 ‖ ro4)
   B. gm (ro2 ‖ ro4)
   C. gm RC/2
   D. RC/(2RE)
   Answer: B. The output current gm vd flows into resistance ro2 ‖ ro4. (Key point: Active load gain)

4. Why does the active load double the gain for equal load resistance?
   A. The tail current doubles
   B. Both halves of the signal current reach the output
   C. The supply voltage doubles
   D. β doubles
   Answer: B. Mirror copies ic1 to the output, adding to the −ic2 drawn from it, giving gm vd. (Key point: Doubling)

## Related in Advanced Electronics

- [Active load doubles differential amplifier gain](https://www.bctengineer.com/question.md?key=semester_4%2Fadvanced_electronics%3Aactive-load-gain-twice-passive) — Advanced Electronics, chapter 1, asked 2×
- [Mirror output current error and Widlar resistance](https://www.bctengineer.com/question.md?key=semester_4%2Fadvanced_electronics%3Amirror-error-widlar-output-resistance) — Advanced Electronics, chapter 1
- [Short note: Differential amplifier with active load](https://www.bctengineer.com/question.md?key=semester_4%2Fadvanced_electronics%3Ashort-note-diff-amp-active-load) — Advanced Electronics, chapter 1
- [Current mirror conditions and Widlar output resistance](https://www.bctengineer.com/question.md?key=semester_4%2Fadvanced_electronics%3Awidlar-essential-conditions-output-resistance) — Advanced Electronics, chapter 1, asked 3×
- [Current mirror advantages and Widlar output resistance](https://www.bctengineer.com/question.md?key=semester_4%2Fadvanced_electronics%3Acurrent-mirror-advantages-widlar) — Advanced Electronics, chapter 1
- [Current mirror output current, finite β effects](https://www.bctengineer.com/question.md?key=semester_4%2Fadvanced_electronics%3Acurrent-mirror-finite-beta) — Advanced Electronics, chapter 1

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- [Insertion gain/loss, design steps, active vs passive](https://www.bctengineer.com/question.md?key=semester_5%2Ffilter_design%3Ainsertion-loss-steps-active-passive) — Filter Design, chapter 1
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