---
title: "Mirror output current error and Widlar resistance"
subject: "Advanced Electronics"
chapter: 1
key: "semester_4/advanced_electronics:mirror-error-widlar-output-resistance"
source: https://www.bctengineer.com/q/semester_4/advanced_electronics/mirror-error-widlar-output-resistance
site: BCT Engineering
---

# Mirror output current error and Widlar resistance

Advanced Electronics · Chapter 1: Operational Amplifier Circuits

- Asked in: 2072 Kartik, 2+5 marks
- Video: [Lec-50 Introduction to Current Mirror Circuit & Advantages | R K Classes | Hindi |](https://www.youtube.com/watch?v=kBQzZ7ZlrQI) — R K Classes
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_4/advanced_electronics/mirror-error-widlar-output-resistance
- Whole chapter: https://www.bctengineer.com/md/semester_4/advanced_electronics/chapter-1

## Question

Why output current of simple mirror circuit is not exactly equal to reference current? Derive the output resistance of Widlar current source.

## Short answer

Output current differs because finite β gives IO = IREF/(1+2/β), Early effect makes IO vary with VCE2, and transistor mismatch exists. Small-signal derivation yields Widlar output resistance Ro ≈ ro(1+gm R'E) ≈ ro(1+gm RE) if RE<<rπ, raised by series feedback.

## Answer

#### Why IO is not exactly equal to IREF
In a simple two-transistor mirror the output current IO is not exactly IREF because:

1. **Finite β (base current):** IREF must supply IC1 plus both base currents:
   IREF = IC + 2IC/β, so **IO = IREF/(1 + 2/β)**. For β = 100, IO is about 2% less than IREF.
2. **Early effect (finite ro):** VCE1 = VBE ≈ 0.7 V but VCE2 is set by the load and is usually larger. Because of base-width modulation, IO = IC1(1 + (VCE2 − VBE)/VA), so IO is slightly larger and changes with output voltage.
3. **Mismatch:** small differences in IS (emitter area, doping) and temperature between Q1 and Q2 make VBE1 = VBE2 give unequal currents.

#### Output resistance of the Widlar current source

```text
  +VCC                 IO (from load)
    |                    |
    R                    |
    | IREF               |
    +------+             |
    |      |             |
    C1     |             C2
  Q1  B----+-------------B  Q2
    E1                   E2
    |                    |
    |                    RE
    |                    |
   GND                  GND
```

DC relation: VBE1 − VBE2 = IO·RE, so IO·RE = VT ln(IREF/IO), giving IO << IREF.

Small-signal model: Q1 is diode-connected, so its resistance is only about 1/gm1 and the base of Q2 is close to ac ground. Apply a test voltage *vx* at the collector of Q2 and let *ix* flow into it.

```text
Emitter node: ix flows into RE ‖ rπ (rπ goes to the
grounded base), so
   ve  = ix (RE ‖ rπ) = ix R'E
Base is grounded:
   vbe = 0 - ve = -ix R'E
Current into collector:
   ix  = gm vbe + (vx - ve)/ro
       = -gm ix R'E + (vx - ix R'E)/ro
Multiply by ro and collect terms:
   vx  = ix ro + ix R'E (1 + gm ro)
   Ro  = vx/ix = ro + R'E (1 + gm ro)
Since gm ro >> 1:
   Ro ≈ ro (1 + gm R'E),   R'E = RE ‖ rπ
```

If RE << rπ, then **Ro ≈ ro(1 + gm RE)**, where gm = IO/VT and ro = VA/IO. A simple mirror has Ro = ro only, so the Widlar source has an output resistance larger by the factor (1 + gm RE). Since gm·RE = IO·RE/VT = ln(IREF/IO), this factor is typically about 4 to 6 (for example, 5.6 when IREF/IO = 100). This is the result of the current-series negative feedback provided by the unbypassed RE: any rise in IO raises the drop across RE, lowers VBE2 and pulls IO back down.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. Why does finite β make IO smaller than IREF?
   A. Q2 saturates
   B. The Early voltage is infinite
   C. IREF also supplies the two base currents
   D. RE drops voltage
   Answer: C. IREF = IC + 2IC/β, so IO = IREF/(1 + 2/β) < IREF. (Key point: Finite β error)

2. Why does the Early effect make IO change with the load?
   A. Because β changes with temperature only
   B. VCE2 differs from VCE1 = VBE, so IC2 = IC1(1 + (VCE2 − VBE)/VA) rises with VCE2
   C. Because RE changes
   D. Because the base current is zero
   Answer: B. Base-width modulation raises IC with VCE; VCE2 is set by the load. (Key point: Early effect)

3. Which relation links IO and IREF in the Widlar source?
   A. IO = IREF·(1 + gm RE)
   B. IO = IREF
   C. IO·RE = VCC − VBE
   D. IO·RE = VT ln(IREF/IO)
   Answer: D. VBE1 − VBE2 = IO·RE and the difference of two log terms gives IO·RE = VT ln(IREF/IO). (Key point: Widlar DC relation)

4. What is the output resistance of the Widlar current source (RE << rπ)?
   A. gm RE
   B. ro/(1 + gm RE)
   C. ro
   D. ro(1 + gm RE)
   Answer: D. The unbypassed RE gives current-series feedback, raising Ro from ro to about ro(1 + gm RE). (Key point: Widlar output resistance)

## Related in Advanced Electronics

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