--- title: "Sample and hold circuit" subject: "Instrumentation I" chapter: 6 key: "semester_4/instrumentation_i:sample-and-hold-circuit" source: https://www.bctengineer.com/q/semester_4/instrumentation_i/sample-and-hold-circuit site: BCT Engineering --- # Sample and hold circuit Instrumentation I · Chapter 6: Digital Instrumentation - Asked in: year not given, 8 marks - Video: [Sample & Hold Circuit using OpAmp (Basics, Circuit, Working & Waveforms) Explained](https://www.youtube.com/watch?v=JJBQcnxM7lI) — Engineering Funda - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_4/instrumentation_i/sample-and-hold-circuit - Whole chapter: https://www.bctengineer.com/md/semester_4/instrumentation_i/chapter-6 ## Question Explain sample and hold circuit with necessary circuit diagrams. ## Short answer A sample-and-hold circuit consists of an input buffer, an analog switch, a hold capacitor and an output buffer. In sample mode the switch closes and the capacitor charges to the input voltage; in hold mode the switch opens and the output stays constant. Key parameters are acquisition time, aperture time and droop rate. ## Answer A **sample-and-hold (S/H) circuit** takes a sample of an analog signal and holds its value constant for the required time. It is used before an ADC so that the input does not change during conversion. #### Basic circuit ```text +----+ SW (FET) +----+ Vin o----->| A1 |------o/ o----+---->| A2 |-----o Vout +----+ ^ | +----+ | === Ch control | (S/H) gnd ``` - A1 is an input buffer (low output impedance, so Ch charges quickly). - SW is an analog switch (MOSFET or JFET) controlled by a logic signal. - Ch is the hold capacitor (low leakage, e.g. polystyrene or Teflon). - A2 is an output buffer with a very high input impedance, so the capacitor does not discharge through it. #### Operation - **Sample mode:** the control is high and the switch is closed. Ch charges through the switch to Vin, and the output follows the input. - **Hold mode:** the control is low and the switch opens. Ch keeps its charge, and the output stays constant at the value it had at the instant the switch opened. ```text control: |‾‾ S ‾‾|__ H __|‾‾ S ‾‾|__ H __| Vout: tracks held tracks held Vin flat Vin flat ``` #### Important parameters - **Acquisition time:** the time needed to charge Ch to the input value within a given accuracy. - **Aperture time:** the delay between the hold command and the switch actually opening. - **Droop rate:** the fall of the voltage across Ch in hold mode due to leakage (dV/dt = Ileak/Ch). - **Feedthrough:** the input signal leaking through the open switch. - **Hold-mode settling time.** A larger Ch lowers the droop but increases the acquisition time, so a compromise is made. A feedback version (with the switch inside the op-amp's feedback loop) improves accuracy. S/H circuits are used in DAS, ADC front ends and for demultiplexing DAC outputs. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. Why is a sample-and-hold circuit used before an ADC? A. To amplify the signal so the ADC reads larger values B. To keep the input constant while the conversion takes place C. To remove noise by averaging many samples D. To convert the analog signal into a digital one Answer: B. The S/H takes a sample and holds it steady so the input does not change during the ADC's conversion time. (Key point: Purpose of S/H) 2. What happens to the switch and the hold capacitor in hold mode? A. The switch stays closed and Ch follows Vin B. The switch closes and Ch discharges fully C. The switch opens and Ch keeps its charge, so Vout stays at the value at the instant of opening D. The switch opens and Vout drops to zero immediately Answer: C. In hold mode the control is low, the switch opens and Ch retains its charge, holding the output constant. (Key point: Sample and hold modes) 3. Why is the output buffer A2 given a very high input impedance? A. So the capacitor does not discharge through the load B. So Ch charges more quickly in sample mode C. So the switch opens faster D. So feedthrough from the input is increased Answer: A. A high-impedance A2 draws almost no current from Ch, preventing the held voltage from leaking away. (Key point: Role of the output buffer A2) 4. What is the trade-off in choosing the hold capacitor Ch? A. Larger Ch increases droop and shortens acquisition time B. Larger Ch lowers droop but increases acquisition time C. Larger Ch lowers both droop and acquisition time D. Ch has no effect on droop, only on aperture time Answer: B. Droop rate is Ileak/Ch, so a larger Ch droops less, but it takes longer to charge, so a compromise is made. (Key point: Choice of Ch) ## Related in other subjects - [Short note: Sample and hold circuit](https://www.bctengineer.com/question.md?key=semester_6%2Fdigital_control_system%3Ashort-note-sample-hold) — Digital Control System, chapter 1 - [Sample and hold: tracking and hold modes](https://www.bctengineer.com/question.md?key=semester_6%2Fdigital_control_system%3Asample-hold-tracking-hold) — Digital Control System, chapter 1, asked 3× - [Sample-and-hold capacitor voltage and advantages](https://www.bctengineer.com/question.md?key=semester_6%2Fdigital_control_system%3Asample-hold-capacitor-voltage) — Digital Control System, chapter 1 - [Importance and operation of sample and hold](https://www.bctengineer.com/question.md?key=semester_6%2Fdigital_control_system%3Aimportance-of-sample-hold) — Digital Control System, chapter 1