--- title: "Internal architecture of 8085" subject: "Microprocessor" chapter: 2 key: "semester_4/microprocessor:8085-architecture" source: https://www.bctengineer.com/q/semester_4/microprocessor/8085-architecture site: BCT Engineering --- # Internal architecture of 8085 Microprocessor · Chapter 2: Programming with 8085 Microprocessor - Asked in: 2071 Magh, 8 marks; 2069 Poush, 8 marks; 2068 Bhadra, 8 marks (asked 3 times) - Video: [Architecture of 8085 Microprocessor: Data Flow and Working Explained | 8085](https://www.youtube.com/watch?v=OK_LudRfBas) — Engineering Funda - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_4/microprocessor/8085-architecture - Whole chapter: https://www.bctengineer.com/md/semester_4/microprocessor/chapter-2 ## Question Draw the internal architecture (block diagram) of 8085 microprocessor and explain each part. ## Short answer The 8085 architecture includes an ALU, accumulator, flag register, six general-purpose registers (B,C,D,E,H,L) usable as pairs, PC, SP, instruction register/decoder, timing and control, interrupt and serial I/O. The ALU performs arithmetic/logic operations, while address/data buffers drive the multiplexed bus. ## Answer The 8085 is an 8-bit microprocessor with a 16-bit address bus, made in NMOS technology, single +5 V supply, 3 MHz (max) clock. Its internal architecture has the following blocks. ```text +--------------------------------------------------+ | Interrupt control | Serial I/O control | | INTR INTA RST TRAP| SID SOD | +--------------------------------------------------+ | Accum.(A) |Temp reg| W | Z | B | C | D | E | | Flags | | | H | L | SP | PC | | \_____ ALU _____/ | Inc/Dec address | | | latch | +--------------------------------------------------+ | Instruction reg -> Decoder -> Timing and control | | ALE RD WR IO/M S0 S1 READY | +--------------------------------------------------+ | Addr buffer (A15-A8) | Addr/Data buffer (AD7-0) | +--------------------------------------------------+ 8-bit internal data bus runs through all ``` #### 1. ALU Performs arithmetic (add, subtract, increment, decrement) and logic (AND, OR, XOR, compare, rotate, complement) operations. One input comes from the accumulator and the other from the temporary register. The result goes back to the accumulator. #### 2. Accumulator (A) and temporary register The 8-bit accumulator holds one operand and the result. The temporary register is invisible to the programmer and holds the second operand during the ALU operation. #### 3. Flag register Five flags: Sign (S), Zero (Z), Auxiliary Carry (AC), Parity (P), Carry (CY). They show the status of the last arithmetic/logic result. #### 4. General purpose registers B, C, D, E, H, L (8-bit each); they work singly or as BC, DE, HL pairs. W and Z are temporary registers used internally by CALL, XCHG etc.; they are not available to the programmer. #### 5. Program Counter (PC) and Stack Pointer (SP) Both are 16-bit. PC holds the address of the next instruction to be fetched. SP holds the address of the top of the stack in memory. #### 6. Increment/Decrement address latch Increments or decrements PC/SP (or register pair) after every fetch, push and pop. #### 7. Instruction register and decoder The opcode fetched is stored in the instruction register (IR) and decoded by the instruction decoder. #### 8. Timing and control unit Generates timing and control signals (ALE, RD, WR, IO/M, S0, S1) and synchronises all operations using the clock from the on-chip clock generator. #### 9. Interrupt control Handles TRAP, RST7.5, RST6.5, RST5.5, INTR and sends INTA. #### 10. Serial I/O control Handles serial data in (SID) and serial data out (SOD) using the RIM and SIM instructions. #### 11. Address buffer and address/data buffer The address buffer drives the higher-order address A15-A8. The address/data buffer drives the multiplexed lines AD7-AD0 (low-order address and data), separated using ALE. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. In the 8085, where do the two ALU inputs come from, and where does the result go? A. From registers B and C; the result goes to register B B. From the accumulator and the flag register; the result goes to the temporary register C. From the accumulator and the temporary register; the result goes back to the accumulator D. From the internal data bus only; the result goes to the instruction register Answer: C. One ALU input is the accumulator and the other is the temporary register, which holds the second operand. The result is stored back in the accumulator. (Key point: ALU takes operands from accumulator and temporary register; result goes to A) 2. What are the W and Z registers in the 8085? A. Temporary registers used internally (e.g. by CALL, XCHG) that the programmer cannot use B. General purpose registers that can be used as the WZ pair in programs C. The high and low bytes of the stack pointer D. Registers that hold the flags during an interrupt Answer: A. W and Z are used internally by instructions such as CALL and XCHG to hold temporary values. No instruction lets the programmer access them. (Key point: W and Z are internal temporary registers, not available to the programmer) 3. Which of these is NOT one of the 8085 flags? A. Auxiliary Carry (AC) B. Parity (P) C. Sign (S) D. Overflow (V) Answer: D. The 8085 has five flags: Sign, Zero, Auxiliary Carry, Parity and Carry. It has no overflow flag. (Key point: 8085 has five flags: S, Z, AC, P, CY) 4. The lines AD7-AD0 carry both the low-order address and data. How are the two separated? A. The address and data are sent on alternate clock edges and the memory decodes them B. ALE goes high in T1 so an external latch holds the low address byte; later the lines carry data C. The IO/M signal switches the lines from address mode to data mode D. The higher-order address buffer A15-A8 carries the low address byte when data is on AD7-AD0 Answer: B. In T1 the low address byte is on AD7-AD0 and ALE is high, so an external latch captures it. After that the same lines carry data. (Key point: AD7-AD0 carry low address and data, separated using ALE) ## Related in Microprocessor - [Internal architecture of 8086](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3A8086-architecture-block-diagram) — Microprocessor, chapter 3, asked 4× - [Microprocessor based system and bus organization](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Amp-based-system-bus-organization) — Microprocessor, chapter 1, asked 5× - [8086 architecture and programmer registers](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3A8086-architecture-registers) — Microprocessor, chapter 3 - [8085 flags and their effect](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3A8085-flags-effect) — Microprocessor, chapter 2, asked 3× - [Programming model of 8085](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3A8085-programming-model) — Microprocessor, chapter 2, asked 2× - [Features and addressing modes of 8085](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3A8085-features-addressing-modes) — Microprocessor, chapter 2 ## Related in other subjects - [MBI block diagram and basic features](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Ambi-block-features) — Instrumentation II, chapter 1, asked 4× - [DMA controller block diagram and transfer](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Adma-controller) — Computer Organization and Architecture, chapter 7, asked 6× - [MBI block diagram, advantages and DMA](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Ambi-block-advantages-dma) — Instrumentation II, chapter 1 - [MBI block diagram and advantages in industry](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Ambi-block-advantages) — Instrumentation II, chapter 1