--- title: "Characteristics and signals of 8085" subject: "Microprocessor" chapter: 2 key: "semester_4/microprocessor:8085-characteristics-signals" source: https://www.bctengineer.com/q/semester_4/microprocessor/8085-characteristics-signals site: BCT Engineering --- # Characteristics and signals of 8085 Microprocessor · Chapter 2: Programming with 8085 Microprocessor - Asked in: 2073 Bhadra, 2+6 marks - Video: [8085 Microprocessor pins and signals](https://www.youtube.com/watch?v=wZ6MbB6Z9a4) — CS LEARNING ARENA - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_4/microprocessor/8085-characteristics-signals - Whole chapter: https://www.bctengineer.com/md/semester_4/microprocessor/chapter-2 ## Question What are the characteristics of 8085 microprocessor? Discuss all the input and output signals that are originated from microprocessor. ## Short answer The 8085 is an 8-bit NMOS microprocessor with 64 KB address space, 256 I/O ports, +5 V supply, on-chip clock, five interrupts, and DMA support. Output signals include A15-A8, AD7-AD0, ALE, RD, WR, IO/M, S1/S0, INTA, HLDA, CLK OUT, RESET OUT, and SOD. ## Answer #### Characteristics of the 8085 - 8-bit microprocessor, NMOS technology, 40-pin DIP. - 8-bit data bus and 16-bit address bus: 64 KB memory; 256 I/O ports (8-bit port address). - Single +5 V supply; on-chip clock generator and oscillator (3 MHz max). - Multiplexed lower address/data bus (AD0-AD7) using ALE. - Five interrupts: TRAP, RST7.5, RST6.5, RST5.5, INTR. All are maskable except TRAP; all are vectored except INTR (the interrupting device supplies the instruction). - Serial I/O using SID and SOD; DMA support with HOLD and HLDA. - 74 instructions (246 opcodes); general registers B, C, D, E, H, L; 16-bit SP and PC. #### Signals generated (output) by the 8085 | Signal | Description | |---|---| | **A15-A8** | Higher-order address lines, unidirectional, output. | | **AD7-AD0** | Multiplexed low-order address and data (bidirectional); address in T1, data after. | | **ALE** | Address Latch Enable; high in T1 so an external latch (74LS373) can save A7-A0. | | **RD** | Active-low read control; the selected memory/I/O puts data on the data bus. | | **WR** | Active-low write control; data on the bus is to be written. | | **IO/M** | High for I/O operation, low for memory operation. | | **S1, S0** | Status; with IO/M define the machine cycle (00 halt, 01 write, 10 read, 11 fetch). | | **INTA** | Interrupt acknowledge, tells the interrupting device the CPU accepted INTR. | | **HLDA** | Hold acknowledge, confirms bus is released to DMA controller. | | **CLK (OUT)** | System clock output for other devices. | | **RESET OUT** | Indicates CPU is being reset; used to reset peripherals. | | **SOD** | Serial output data. | (Input signals are HOLD, READY, INTR, TRAP, RST7.5/6.5/5.5, SID, RESET IN, X1, X2.) ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. Why can the 8085 address 64 KB of memory but only 256 I/O ports? A. Memory uses a 20-bit address while I/O uses a 16-bit address B. Memory addresses are 16 bits (2^16 = 64K) while I/O port addresses are 8 bits (2^8 = 256) C. The data bus is 8 bits, which limits memory to 64 KB D. I/O ports share the multiplexed AD0-AD7 lines, so only half the addresses are available Answer: B. The 16-bit address bus gives 2^16 = 65,536 memory locations (64 KB). IN/OUT use an 8-bit port address, which gives 256 ports. (Key point: 16-bit address bus gives 64 KB; 8-bit port address gives 256 I/O ports) 2. What is the purpose of the ALE signal in the 8085? A. It enables the higher-order address lines A15-A8 B. It tells memory to put data on the bus during a read C. It goes high in T1 so an external latch (such as 74LS373) can save the low-order address A7-A0 from the multiplexed AD7-AD0 lines D. It acknowledges that the bus has been released to a DMA controller Answer: C. AD7-AD0 carry the low address byte in T1 and data after that. ALE is high in T1 so an external latch holds A7-A0 while the lines are used for data. (Key point: ALE is high in T1 so an external latch saves A7-A0) 3. During an opcode fetch machine cycle, what are IO/M, S1 and S0? A. IO/M = 1, S1 = 1, S0 = 1 B. IO/M = 0, S1 = 1, S0 = 0 C. IO/M = 0, S1 = 0, S0 = 1 D. IO/M = 0, S1 = 1, S0 = 1 Answer: D. An opcode fetch is a memory operation (IO/M = 0) and its status is S1 S0 = 11. 10 is memory read, 01 is write and 00 is halt. (Key point: IO/M, S1, S0 define the machine cycle (11 = opcode fetch)) 4. Which statement about the 8085 interrupts is correct? A. TRAP is non-maskable, and INTR is non-vectored (the interrupting device supplies the instruction) B. All five interrupts are maskable and vectored C. INTR is non-maskable, and TRAP is non-vectored D. RST7.5 is non-maskable because it has the highest priority among RST interrupts Answer: A. All interrupts are maskable except TRAP, and all are vectored except INTR, where the device supplies the instruction after INTA. (Key point: TRAP is the only non-maskable interrupt; INTR is the only non-vectored one) ## Related in Microprocessor - [Important pin signals of 8085](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3A8085-important-pin-signals) — Microprocessor, chapter 2 - [Address decoding for input and output ports](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-input-output-port-block-decoder) — Microprocessor, chapter 4 - [Internal architecture of 8085](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3A8085-architecture) — Microprocessor, chapter 2, asked 3× - [8085 flags and their effect](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3A8085-flags-effect) — Microprocessor, chapter 2, asked 3× - [Programming model of 8085](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3A8085-programming-model) — Microprocessor, chapter 2, asked 2× - [Features and addressing modes of 8085](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3A8085-features-addressing-modes) — Microprocessor, chapter 2 ## Related in other subjects - [CE configuration input/output characteristics](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Ace-npn-characteristics) — Basic Electronics Engineering, chapter 3, asked 3× - [Slew-rate check for four input signals](https://www.bctengineer.com/question.md?key=semester_4%2Fadvanced_electronics%3Aslew-rate-multiple-signals) — Advanced Electronics, chapter 2 - [Periodic and non-periodic signals; LTI output is convolution](https://www.bctengineer.com/question.md?key=semester_6%2Fcommunication_systems%3Aperiodic-nonperiodic-convolution) — Communication Systems, chapter 1 - [Output of e^(−2t)u(t) to a rectangular input](https://www.bctengineer.com/question.md?key=semester_4%2Fsignals_and_systems%3Aconvolution-exponential-rect-input) — Signals and Systems, chapter 5, asked 4×