--- title: "8085 flags and their effect" subject: "Microprocessor" chapter: 2 key: "semester_4/microprocessor:8085-flags-effect" source: https://www.bctengineer.com/q/semester_4/microprocessor/8085-flags-effect site: BCT Engineering --- # 8085 flags and their effect Microprocessor · Chapter 2: Programming with 8085 Microprocessor - Asked in: 2073 Magh, 1+2+5 marks; 2073 Bhadra, 4 marks; 2072 Magh, 1+2+5 marks (asked 3 times) - Video: [Lec-6: Types of Flag Register in 8085 Microprocessor | Auxiliary carry | Parity | Carry flag](https://www.youtube.com/watch?v=rlcBbFa9A6M) — Gate Smashers - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_4/microprocessor/8085-flags-effect - Whole chapter: https://www.bctengineer.com/md/semester_4/microprocessor/chapter-2 ## Question What is flag? Discuss about 8085 associated flags. Along with suitable examples show how these flags are affected by arithmetic and logical group of instructions. ## Short answer Flags are 1-bit status flip-flops in the 8085: Sign, Zero, Auxiliary Carry, Parity, Carry. Arithmetic instructions (ADD, SUB) affect all five; logical instructions set CY=0 and AC=0 or 1 depending on operation, while S,Z,P reflect result; XRA A clears A and CY. ## Answer #### Flag A **flag** is a 1-bit flip-flop which shows a condition produced by the last arithmetic or logical operation. The flags are stored in the 8-bit flag register, and conditional jump/call/return instructions test them. #### 8085 flags ```text D7 D6 D5 D4 D3 D2 D1 D0 S Z X AC X P X CY (X = undefined) ``` | Flag | Set (=1) when | Reset (=0) when | |---|---|---| | **S** Sign | Bit D7 of result is 1 (negative) | D7 is 0 | | **Z** Zero | Result is 00H | Result is non-zero | | **AC** Auxiliary carry | Carry from bit D3 to D4 | No such carry | | **P** Parity | Result has an even number of 1s | Odd number of 1s | | **CY** Carry | Carry out from D7 (or borrow in subtraction) | No carry/borrow | #### Effect of arithmetic group (ADD, ADI, SUB, CMP, etc.) All five flags are affected. Example 1: A = 9AH, `ADI 76H` ```text 1001 1010 (9AH) + 0111 0110 (76H) = 1 0001 0000 -> A = 10H ``` CY = 1 (carry out), AC = 1 (A+6 = 10H, carry from low nibble), S = 0, Z = 0, P = 0 (one 1 only, odd). Example 2: A = 80H, `ADI 80H` gives A = 00H: CY = 1, Z = 1, P = 1, S = 0, AC = 0. Example 3: A = 7FH, `ADI 01H` gives A = 80H: S = 1, AC = 1, CY = 0, Z = 0, P = 0. `INR` and `DCR` affect all flags except CY. `INX`, `DCX`, `LXI`, `MOV`, `PUSH`, `POP` affect no flags. `DAD` affects only CY. #### Effect of logical group (ANA, ANI, ORA, ORI, XRA, XRI, CMA, CMP) - `ANA / ANI`: CY = 0 and AC = 1 always; S, Z, P depend on the result. - `ORA / ORI / XRA / XRI`: CY = 0 and AC = 0; S, Z, P depend on the result. - `CMA`: no flags change. `CMP`: flags set as for subtraction (Z = 1 if equal, CY = 1 if A < operand). - Rotate instructions (`RLC`, `RRC`, `RAL`, `RAR`) affect only CY. Example 4: A = F0H, B = 0FH, `ANA B` gives A = 00H: Z = 1, P = 1, S = 0, CY = 0, AC = 1. Example 5: A = 85H, `ORA A` gives A = 85H: S = 1, Z = 0, P = 0 (three 1s), CY = 0, AC = 0. Example 6: `XRA A` clears A: A = 00H, Z = 1, P = 1, CY = 0, AC = 0 (a common way to clear A and CY). ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. A = 80H and ADI 80H is executed, giving A = 00H. Which set of flags is correct? A. CY = 0, Z = 1, P = 0, S = 0 B. CY = 1, Z = 0, P = 0, S = 1 C. CY = 1, Z = 1, P = 1, S = 0 D. CY = 1, Z = 1, P = 0, S = 0 Answer: C. 80H + 80H = 1 00H, so a carry leaves D7 (CY = 1) and the result is 00H (Z = 1). 00H has zero 1s, which is an even count, so P = 1, and D7 = 0 gives S = 0. (Key point: Z = 1 for a 00H result; P = 1 for an even number of 1s) 2. After ANA or ANI, what are CY and AC, whatever the result? A. CY = 1 and AC = 0 B. CY = 0 and AC = 1 C. CY = 0 and AC = 0 D. CY and AC are left unchanged Answer: B. In the 8085, the AND instructions always reset CY and set AC. Only S, Z and P depend on the result. (OR and XOR clear both CY and AC.) (Key point: ANA/ANI always give CY = 0 and AC = 1) 3. Which statement about flag effects is correct? A. INX and DCX affect all flags except CY B. INR and DCR affect only the CY flag C. MOV and PUSH affect the Z and S flags D. INR/DCR affect all flags except CY; INX/DCX affect none Answer: D. INR/DCR change S, Z, AC and P but leave CY alone. The 16-bit INX/DCX, like MOV, LXI, PUSH and POP, change no flags. (Key point: INR/DCR affect all flags except CY; INX/DCX affect none) 4. A = 85H (1000 0101) and ORA A is executed. What is the parity flag? A. P = 0, because the result has three 1s (an odd count) B. P = 1, because the result is non-zero C. P = 1, because the result has three 1s D. P is unchanged, because ORA A does not change A Answer: A. P = 1 only when the result has an even number of 1s. 85H has three 1s (odd), so P = 0. ORA A still updates S, Z and P and clears CY and AC. (Key point: P is set by an even count of 1s, not by a non-zero result) ## Related in Microprocessor - [Classification of 8085 instructions](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3A8085-instruction-classification) — Microprocessor, chapter 2 - [RST instructions in 8085](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Arst-instructions) — Microprocessor, chapter 2 - [PC and SP in CALL, RET, PUSH, POP](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Apc-sp-call-ret-push-pop) — Microprocessor, chapter 2 ## Related in other subjects - [Data manipulation: logical and bit instructions](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Alogical-bit-instr) — Computer Organization and Architecture, chapter 2, asked 2× - [Arithmetic versus logical IF](https://www.bctengineer.com/question.md?key=semester_1%2Fcomputer_programming%3Afortran-arithmetic-vs-logical-if) — Computer Programming, chapter 11, asked 3× - [Pile capacity in sand, group effect, load test](https://www.bctengineer.com/question.md?key=semester_5%2Ffoundation_engineering%3Apile-capacity-sand-group-load-test) — Foundation Engineering, chapter 8 - [Need of logical clock synchronization](https://www.bctengineer.com/question.md?key=semester_7%2Fdistributed_system%3Alogical-clock-sync-need) — Distributed System, chapter 5