--- title: "Important pin signals of 8085" subject: "Microprocessor" chapter: 2 key: "semester_4/microprocessor:8085-important-pin-signals" source: https://www.bctengineer.com/q/semester_4/microprocessor/8085-important-pin-signals site: BCT Engineering --- # Important pin signals of 8085 Microprocessor · Chapter 2: Programming with 8085 Microprocessor - Asked in: 2068 Magh, 8 marks - Video: [Lec-3: 8085 | 40-pin diagram | External Architecture in Hindi](https://www.youtube.com/watch?v=llh4rkvj2OA) — Gate Smashers - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_4/microprocessor/8085-important-pin-signals - Whole chapter: https://www.bctengineer.com/md/semester_4/microprocessor/chapter-2 ## Question Explain the important pin signals of 8085 microprocessor. ## Short answer Key pins: A15-A8 address, AD7-AD0 multiplexed address/data, ALE latch enable, RD/WR control, IO/M and S1/S0 status, READY wait input, TRAP/RST/INTR interrupts with INTA, HOLD/HLDA DMA, SID/SOD serial, RESET IN/OUT, X1/X2 and CLK OUT, Vcc/Vss. ## Answer The 8085 is a 40-pin IC. Its signals are grouped as follows. #### 1. Address and data bus - **A15-A8**: higher-order address bus, output, unidirectional. - **AD7-AD0**: lower-order address bus multiplexed with the data bus. Address during T1, data in T2-T3. - **ALE** (Address Latch Enable): output pulse in T1, to latch the low byte of the address in an external latch. #### 2. Control and status signals - **RD**: active low, memory/I/O read. - **WR**: active low, memory/I/O write. - **IO/M**: high = I/O operation, low = memory operation. - **S1, S0**: status signals; 00 = halt, 01 = write, 10 = read, 11 = opcode fetch. - **READY**: input; if low, the CPU waits (wait states) for a slow device. #### 3. Interrupt signals - **TRAP**: non-maskable, highest priority, edge and level triggered; vector 0024H. - **RST7.5, RST6.5, RST5.5**: maskable, vectored interrupts (3CH, 34H, 2CH). - **INTR**: general-purpose maskable interrupt; non-vectored, device supplies the instruction. - **INTA**: output, acknowledges INTR. #### 4. DMA signals - **HOLD**: input, DMA controller asks for the buses. - **HLDA**: output, CPU acknowledges and releases the buses. #### 5. Serial I/O - **SID**: serial input data (read by RIM). - **SOD**: serial output data (set by SIM). #### 6. Reset and clock - **RESET IN**: input, active low; resets PC to 0000H and clears interrupt enable. - **RESET OUT**: output, resets peripheral devices. - **X1, X2**: connections for crystal, RC or LC; internal clock = f/2. - **CLK OUT**: system clock output. #### 7. Power supply - **Vcc** (+5 V) and **Vss** (ground). ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What is the job of the ALE signal? A. It enables the higher-order address bus A15-A8 B. It tells memory that a read operation is in progress C. It is a pulse in T1 that lets an external latch hold the low-order address byte from AD7-AD0 D. It acknowledges the INTR interrupt Answer: C. AD7-AD0 is multiplexed. ALE goes high in T1 so an external latch can capture the low address byte before the lines carry data. (Key point: ALE pulses in T1 to latch the low address byte) 2. If IO/M = 0, S1 = 1 and S0 = 0, what operation is the 8085 doing? A. Opcode fetch B. Memory read C. Memory write D. I/O read Answer: B. IO/M = 0 means a memory operation, and S1 S0 = 10 means read. So it is a memory read; opcode fetch would be S1 S0 = 11. (Key point: S1 S0: 00 halt, 01 write, 10 read, 11 opcode fetch) 3. Which statement about TRAP is correct? A. It is maskable and has the lowest priority B. It is non-vectored; the device supplies the instruction C. It is level triggered only and vectors to 003CH D. It is non-maskable, has the highest priority, is edge and level triggered, and vectors to 0024H Answer: D. TRAP cannot be masked, has the highest priority, needs both edge and level triggering, and jumps to 0024H. 003CH is the vector of RST7.5. (Key point: TRAP is non-maskable, highest priority, edge and level triggered, vector 0024H) 4. A DMA controller makes HOLD high. What does the 8085 do? A. It makes HLDA high and releases the address, data and control buses B. It makes INTA low and reads an instruction from the DMA controller C. It resets PC to 0000H D. It inserts wait states until HOLD goes low, keeping control of the buses Answer: A. HOLD is the DMA request for the buses. The CPU answers with HLDA and gives up the buses so the DMA controller can use them. (Key point: HOLD/HLDA are DMA signals: CPU releases the buses) ## Related in Microprocessor - [Characteristics and signals of 8085](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3A8085-characteristics-signals) — Microprocessor, chapter 2 - [Interrupts and handling with single INTR pin](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Ainterrupt-importance-single-intr) — Microprocessor, chapter 5 - [Internal architecture of 8085](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3A8085-architecture) — Microprocessor, chapter 2, asked 3× - [8085 flags and their effect](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3A8085-flags-effect) — Microprocessor, chapter 2, asked 3× - [Programming model of 8085](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3A8085-programming-model) — Microprocessor, chapter 2, asked 2× - [Features and addressing modes of 8085](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3A8085-features-addressing-modes) — Microprocessor, chapter 2 ## Related in other subjects - [8-channel ADC interface with 8255 and 8085](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aadc8-8255-problem) — Instrumentation II, chapter 4 - [12-bit DAC with 8085](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Adac12-with-8085) — Instrumentation II, chapter 4, asked 2× - [Memory-mapped I/O design for 8085](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Amemmapped-io-design-1000h) — Instrumentation II, chapter 2 - [Interfacing: 512-byte RAM with 8085](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Arag-ram-512-interface) — Instrumentation II, chapter 2