--- title: "Interrupt pins of 8085" subject: "Microprocessor" chapter: 5 key: "semester_4/microprocessor:8085-interrupt-pins" source: https://www.bctengineer.com/q/semester_4/microprocessor/8085-interrupt-pins site: BCT Engineering --- # Interrupt pins of 8085 Microprocessor · Chapter 5: Interrupt Operations - Asked in: 2073 Bhadra, 6 marks - Video: [Interrupts in 8085 microprocessor | COA | Lec-74 | Bhanu Priya](https://www.youtube.com/watch?v=79icCUmqyPc) — Education 4u - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_4/microprocessor/8085-interrupt-pins - Whole chapter: https://www.bctengineer.com/md/semester_4/microprocessor/chapter-5 ## Question Explain how different interrupt pins of 8085 are used. ## Short answer TRAP (non-maskable, edge+level, vector 0024H), RST 7.5 (maskable, edge, 003CH), RST 6.5 (level, 0034H), RST 5.5 (level, 002CH), and INTR (maskable, vector supplied externally via INTA'). INTA' acknowledges INTR. Maskable interrupts controlled by DI/EI and SIM masks. ## Answer The 8085 has five hardware interrupt inputs (TRAP, RST 7.5, RST 6.5, RST 5.5, INTR) and one output INTA' for acknowledgement. | Pin | Type | Trigger | Vector address | Priority | |---|---|---|---|---| | TRAP | Non-maskable | Rising edge **and** high level | 0024H | 1 (highest) | | RST 7.5 | Maskable | Rising edge (latched internally) | 003CH | 2 | | RST 6.5 | Maskable | High level | 0034H | 3 | | RST 5.5 | Maskable | High level | 002CH | 4 | | INTR | Maskable | High level | Given by the device | 5 (lowest) | #### Use of each pin - **TRAP:** used for serious events (power failure, bus error). It is not affected by DI or SIM masks. It must stay high until acknowledged, which avoids false triggering by noise. - **RST 7.5:** a rising edge sets an internal flip-flop, so a short pulse is remembered until it is serviced. The flip-flop can be reset by the SIM instruction (R7.5 bit) and the request can be masked using M7.5. - **RST 6.5 and RST 5.5:** level-sensitive, so the input must remain high until the 8085 samples it. They can be masked with the SIM instruction. - **INTR:** a general-purpose interrupt, used with an external interrupt controller (8259). When it is accepted, the 8085 sends INTA'. The external hardware places an instruction (an RST n opcode, or CALL with an address) on the data bus, and the 8085 executes it. So the vector is chosen by the device. - **INTA':** output. It tells the requesting device that INTR is accepted so the device can place the opcode on the bus. RST 7.5/6.5/5.5 and TRAP do not use INTA'; they have internal vectors. All maskable interrupts are disabled by DI and by reset; EI enables them. When an interrupt is accepted, further maskable interrupts are disabled until EI is executed in the ISR. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What is the priority order of the 8085 interrupts from highest to lowest? A. TRAP, RST 7.5, RST 6.5, RST 5.5, INTR B. INTR, RST 5.5, RST 6.5, RST 7.5, TRAP C. RST 7.5, RST 6.5, RST 5.5, TRAP, INTR D. TRAP, INTR, RST 7.5, RST 6.5, RST 5.5 Answer: A. TRAP has the highest priority, then RST 7.5, 6.5, 5.5, and INTR is lowest. (Key point: Priority order) 2. Why can a short pulse on RST 7.5 still be serviced? A. It is level-sensitive and ignores noise B. A rising edge sets an internal flip-flop that remembers the request C. It is non-maskable like TRAP D. The INTA' signal latches it externally Answer: B. RST 7.5 is rising-edge triggered and latched internally, so a short pulse is remembered until serviced. (Key point: RST 7.5 trigger) 3. Which statement about TRAP is correct? A. It can be masked by SIM B. It is disabled by DI C. It is not affected by DI or SIM masks and needs rising edge and high level D. It is level-sensitive only and uses INTA' Answer: C. TRAP is non-maskable. Requiring both edge and level helps avoid false triggering by noise. (Key point: TRAP characteristics) 4. How does the 8085 get the ISR address for INTR? A. The device places an RST n opcode or CALL instruction on the bus after INTA' B. It is fixed at 0024H C. It is read from an interrupt vector table at 4 x n D. It is read from the SIM register Answer: A. INTR has no fixed vector; the device decides after receiving INTA'. (Key point: INTR vector) ## Related in Microprocessor - [Interrupt vs polling; interrupts in 8085](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Ainterrupt-vs-polling-8085) — Microprocessor, chapter 5 - [Uses of ALE, IO/M, READY, RD pins](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3A8085-pin-uses-ale-iom) — Microprocessor, chapter 2 - [RIM instruction in 8085](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3A8085-rim) — Microprocessor, chapter 5 - [Interrupt vector table and its use](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aivt-interrupt-handling) — Microprocessor, chapter 5, asked 3× ## Related in other subjects - [8-channel ADC interface with 8255 and 8085](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aadc8-8255-problem) — Instrumentation II, chapter 4