--- title: "Uses of ALE, IO/M, READY, RD pins" subject: "Microprocessor" chapter: 2 key: "semester_4/microprocessor:8085-pin-uses-ale-iom" source: https://www.bctengineer.com/q/semester_4/microprocessor/8085-pin-uses-ale-iom site: BCT Engineering --- # Uses of ALE, IO/M, READY, RD pins Microprocessor · Chapter 2: Programming with 8085 Microprocessor - Asked in: 2070 Bhadra, 5 marks - Video: [ALE, IO/M, RD, WR, S1, S0 || Internally Generated Signals || MICROPROCESSOR 8085](https://www.youtube.com/watch?v=ih1sOQy8DvA) — The Learner's Channel - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_4/microprocessor/8085-pin-uses-ale-iom - Whole chapter: https://www.bctengineer.com/md/semester_4/microprocessor/chapter-2 ## Question Write the use of following pins of 8085 microprocessor. ALE, IO/M, READY, RD, AD0-AD7. ## Short answer ALE latches the low address from AD7-AD0 during T1. IO/M selects I/O (high) or memory (low). READY inserts wait states when low. RD reads data from memory or I/O. AD0-AD7 carry the low address in T1 and data in other T-states. ## Answer | Pin | Use | |---|---| | **ALE** | Address Latch Enable, an output. It goes high during T1 of every machine cycle, which tells that AD7-AD0 carry the low-order address. An external latch (74LS373) uses it to hold the address, so the lines can then carry data. | | **IO/M** | Output that separates memory and I/O operations. High means the I/O port is addressed (IN, OUT); low means memory is addressed. Combined with RD and WR it forms MEMR, MEMW, IOR and IOW control signals. | | **READY** | Input used to interface slow memory or peripherals. The CPU samples it in T2; if it is low, the CPU inserts wait states (T-states without action) until the device is ready, then the cycle continues. | | **RD** | Active-low output. Low shows the selected memory location or I/O port should place its data on the data bus, so the CPU reads it. | | **AD0-AD7** | Multiplexed bidirectional lines. During T1 they carry the low-order address A0-A7; in the remaining T-states they carry the 8-bit data (input in read, output in write). | Example: in a memory read machine cycle, ALE = 1 in T1 with AD7-AD0 = A7-A0; ALE = 0 afterwards; IO/M = 0; RD goes low in T2-T3; the data is read on AD7-AD0 at the end of T3. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What is the role of ALE in a machine cycle? A. It goes low in T2 to enable reading from memory B. It stays high through the whole cycle while data is on the bus C. It is an input from memory telling the CPU the address is latched D. It goes high in T1 so an external latch can hold A7-A0 from AD7-AD0 Answer: D. ALE is an output that is high only in T1, when AD7-AD0 carry A7-A0. A latch such as the 74LS373 holds that address, which frees the lines to carry data later in the cycle. It is not an input from memory. (Key point: ALE goes high in T1 so the low address byte can be latched) 2. During the I/O write cycle of OUT 80H, what is the IO/M signal? A. High, because an I/O port is addressed B. Low, because the CPU is writing data C. Low, because the port address is only 8 bits D. It floats, because RD and WR choose the device Answer: A. IO/M high means an I/O port is addressed (as in IN and OUT), and low means memory is addressed. It is combined with WR to form the IOW signal. (Key point: IO/M = 1 for I/O operations, 0 for memory) 3. What happens if a slow memory keeps READY low when the CPU samples it? A. The CPU aborts the cycle and fetches the next instruction B. The CPU raises a TRAP interrupt C. The CPU inserts wait states until READY goes high, then continues the cycle D. The CPU reads whatever is on the data bus immediately Answer: C. READY is an input sampled in T2. While it is low, the CPU adds wait states that do no work, so a slow device has time to respond. The cycle completes once READY is high. (Key point: READY is sampled in T2; if low, wait states are inserted) 4. Why are AD0-AD7 called multiplexed lines? A. They carry the high-order address A8-A15 and data at the same time B. They carry the low-order address A0-A7 during T1 and 8-bit data in the remaining T-states C. They are output-only lines shared between memory and I/O D. They carry status signals S0 and S1 along with the data Answer: B. The same 8 lines carry A0-A7 in T1 (marked by ALE) and then the data byte. They are bidirectional: input during a read, output during a write. (Key point: AD0-AD7 are multiplexed: address in T1, data afterwards) ## Related in Microprocessor - [Interrupt pins of 8085](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3A8085-interrupt-pins) — Microprocessor, chapter 5 - [RST instructions in 8085](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Arst-instructions) — Microprocessor, chapter 2 - [Internal architecture of 8085](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3A8085-architecture) — Microprocessor, chapter 2, asked 3× - [8085 flags and their effect](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3A8085-flags-effect) — Microprocessor, chapter 2, asked 3× - [Programming model of 8085](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3A8085-programming-model) — Microprocessor, chapter 2, asked 2× - [Features and addressing modes of 8085](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3A8085-features-addressing-modes) — Microprocessor, chapter 2 ## Related in other subjects - [8-channel ADC interface with 8255 and 8085](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aadc8-8255-problem) — Instrumentation II, chapter 4 - [Microprocessor vs microcontroller; 8051 addressing](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3A8051-addressing-modes-micro-vs-processor) — Embedded System, chapter 9 - [12-bit DAC with 8085](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Adac12-with-8085) — Instrumentation II, chapter 4, asked 2× - [Memory-mapped I/O design for 8085](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Amemmapped-io-design-1000h) — Instrumentation II, chapter 2