---
title: "RIM instruction in 8085"
subject: "Microprocessor"
chapter: 5
key: "semester_4/microprocessor:8085-rim"
source: https://www.bctengineer.com/q/semester_4/microprocessor/8085-rim
site: BCT Engineering
---

# RIM instruction in 8085

Microprocessor · Chapter 5: Interrupt Operations

- Asked in: 2075 Baisakh, 4 marks
- Video: [SIM and RIM Instructions in Microprocessor 8085: Understanding SIM and RIM Commands](https://www.youtube.com/watch?v=Ns0T0uEzHnU) — Engineering Funda
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_4/microprocessor/8085-rim
- Whole chapter: https://www.bctengineer.com/md/semester_4/microprocessor/chapter-5

## Question

Describe the operation of interrupt instruction RIM in 8085 microprocessor.

## Short answer

RIM (opcode 20H) loads accumulator with interrupt mask status, pending interrupts (I7.5–I5.5), IE flag, and SID input. Used to read serial data and poll mask/pending conditions without affecting flags.

## Answer

**RIM (Read Interrupt Mask)** is a 1-byte instruction (opcode 20H, 4 T-states). It loads the accumulator with the status of the interrupt masks, the pending interrupts, the interrupt enable flip-flop and the serial input data. It affects no flags.

#### Accumulator format after RIM

| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
|---|---|---|---|---|---|---|---|
| SID | I7.5 | I6.5 | I5.5 | IE | M7.5 | M6.5 | M5.5 |

- **SID (D7):** the bit present on the serial input pin at that moment.
- **I7.5, I6.5, I5.5 (D6–D4):** 1 means an interrupt request is pending at that line.
- **IE (D3):** 1 means maskable interrupts are enabled (EI executed).
- **M7.5, M6.5, M5.5 (D2–D0):** 1 means that interrupt is masked (disabled).

#### Uses

- To read serial input data (SID) from a device.
- To check the present mask condition before changing it with SIM, so other mask bits are not disturbed.
- To read which RST interrupts are pending. This allows polling of RST 5.5/6.5/7.5 inputs when interrupts are disabled.

#### Example

```text
RIM          ; A <- status
ANI 08H      ; test IE bit (D3)
JZ  NOINT    ; if 0, interrupts are disabled
```

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. What does RIM do?
   A. Loads the accumulator with mask status, pending interrupts, IE and serial input data
   B. Sets the interrupt masks from the accumulator
   C. Enables all maskable interrupts
   D. Resets the RST 7.5 flip-flop
   Answer: A. RIM reads status into A; it is SIM that sets masks. (Key point: RIM function)

2. After RIM, what does bit D3 (IE) = 1 mean?
   A. RST 7.5 is masked
   B. Maskable interrupts are enabled
   C. A serial input bit is present
   D. An RST 5.5 request is pending
   Answer: B. The IE bit shows the state of the interrupt enable flip-flop, set by EI. (Key point: Accumulator bit D3)

3. Which bits of the accumulator after RIM show pending RST requests?
   A. D2, D1, D0
   B. D7 only
   C. D6, D5, D4 (I7.5, I6.5, I5.5)
   D. D3 only
   Answer: C. I7.5, I6.5 and I5.5 in D6-D4 show pending requests; D2-D0 are the mask bits. (Key point: Pending interrupts)

4. Why is RIM used before changing masks with SIM?
   A. To read the present mask condition so other mask bits are not disturbed
   B. To clear the flags
   C. To disable TRAP
   D. To load the stack pointer
   Answer: A. Reading the current masks lets you change one without altering the rest. (Key point: Use of RIM before SIM)

## Related in Microprocessor

- [Interrupt pins of 8085](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3A8085-interrupt-pins) — Microprocessor, chapter 5
- [Interrupt vs polling; interrupts in 8085](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Ainterrupt-vs-polling-8085) — Microprocessor, chapter 5
- [EI, DI, SIM, RIM and ISR address](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aei-di-sim-rim-vector-address) — Microprocessor, chapter 5
- [RTL for LXI instruction](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Artl-lxi-instruction) — Microprocessor, chapter 1, asked 3×
- [Instruction and data format, addressing modes](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3A8085-instruction-data-format-addressing) — Microprocessor, chapter 2, asked 2×
- [Interrupt processing in 8086](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Ainterrupt-processing-8086) — Microprocessor, chapter 5, asked 3×

## Related in other subjects

- [Instruction cycle state diagram with interrupt](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Ainstr-cycle) — Computer Organization and Architecture, chapter 1, asked 6×
- [Datapath operation and instruction cycles](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Adatapath-operation-instruction-cycles) — Embedded System, chapter 2
- [Interrupt-driven I/O with vectored interrupt](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avectored-interrupt-io-flow) — Embedded System, chapter 5, asked 3×
- [LD instruction under addressing modes](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Ald-addressing-modes) — Computer Organization and Architecture, chapter 2