---
title: "8086 architecture and programmer registers"
subject: "Microprocessor"
chapter: 3
key: "semester_4/microprocessor:8086-architecture-registers"
source: https://www.bctengineer.com/q/semester_4/microprocessor/8086-architecture-registers
site: BCT Engineering
---

# 8086 architecture and programmer registers

Microprocessor · Chapter 3: Programming with 8086 Microprocessor

- Asked in: 2072 Magh, 8 marks
- Video: [Architecture of 8086 Microprocessor: Detailed Block Diagram and Data Flow Model 8086](https://www.youtube.com/watch?v=Uuxa90Xl4Rs) — Engineering Funda
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_4/microprocessor/8086-architecture-registers
- Whole chapter: https://www.bctengineer.com/md/semester_4/microprocessor/chapter-3

## Question

Draw the internal architecture of 8086 microprocessor. Explain the function of each register accessible to programmer.

## Short answer

The 8086 has a BIU (segment registers CS,DS,SS,ES; IP; address adder; queue) and an EU (AX,BX,CX,DX; SP,BP,SI,DI; ALU, flags, control) working in parallel. Programmer's registers: AX (accumulator, I/O), BX (base), CX (count), DX (I/O, mul/div), SP (stack top), BP (stack parameters), SI (source index), DI (destination), segment registers, IP, and flags.

## Answer

```text
 +---------------- BIU ----------------+
 |  CS   DS   SS   ES   (segment regs) |
 |  IP  (instruction pointer)          |
 |  Address adder  -> 20-bit address   |
 |  6-byte instruction queue           |
 |  Bus control logic                  |
 +------------------+------------------+
                    | internal bus
 +------------------+------------------+
 |  AX BX CX DX  (general registers)   |
 |  SP BP SI DI  (pointer/index)       |
 |  ALU      FLAG register             |
 |  Control unit + instruction decoder |
 +---------------- EU -----------------+
   BIU <-> external bus: AD0-AD15, A16-A19, control
```

The 8086 has two units: the **BIU** (fetches instructions, forms 20-bit addresses, handles the bus; contains segment registers, IP, address adder and the 6-byte queue) and the **EU** (decodes and executes; contains general registers, ALU, flags and control unit). They work in parallel.

#### Registers accessible to the programmer
**1. General purpose registers (16-bit, splittable into 8-bit halves)**
- **AX (AH/AL), accumulator:** arithmetic, logic, I/O (IN/OUT), MUL/DIV, string operations.
- **BX (BH/BL), base:** holds an offset address of data; used in XLAT.
- **CX (CH/CL), count:** loop counter for LOOP, count for shifts (CL) and REP.
- **DX (DH/DL), data:** I/O port address, high word of 32-bit multiply/divide result.

**2. Pointer and index registers**
- **SP:** stack pointer, offset of the top of stack (in SS).
- **BP:** base pointer, offset used to access stack-resident data/parameters.
- **SI:** source index for string and indexed addressing (DS:SI).
- **DI:** destination index (ES:DI for strings).

**3. Segment registers**
- **CS:** code segment base. **DS:** data segment base. **SS:** stack segment base. **ES:** extra segment base (string destination).

**4. Instruction pointer (IP):** offset of the next instruction within CS; not directly accessed but changed by jumps and calls.

**5. Flag register:** six status flags (CF, PF, AF, ZF, SF, OF) and three control flags (TF, IF, DF).

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. Which registers belong to the BIU?
   A. AX, BX, CX, DX
   B. CS, DS, SS, ES and IP
   C. SP, BP, SI, DI
   D. Flags only
   Answer: B. The BIU holds segment registers and IP; general and pointer/index registers are in the EU. (Key point: BIU registers)

2. What is AX (accumulator) used for?
   A. Arithmetic, logic, IN/OUT, MUL/DIV and string operations
   B. Count only
   C. Stack top
   D. Segment base
   Answer: A. AX is the main arithmetic and I/O register. (Key point: AX use)

3. Which pair is correct for string operations?
   A. Source DS:SI, destination ES:DI
   B. Source ES:DI, destination DS:SI
   C. Source SS:SP
   D. Both use CS
   Answer: A. SI is the source index, DI the destination index. (Key point: SI and DI)

4. What does IP hold?
   A. Offset of the next instruction within CS
   B. Top of stack
   C. Port address
   D. Result of ALU
   Answer: A. IP is changed by jumps and calls but not directly accessed. (Key point: IP)

## Related in Microprocessor

- [Internal architecture of 8086](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3A8086-architecture-block-diagram) — Microprocessor, chapter 3, asked 4×
- [8086 speed over 8-bit; major registers](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3A8086-faster-registers) — Microprocessor, chapter 3
- [Accumulator based and register based architecture](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aaccumulator-register-based-architecture) — Microprocessor, chapter 6, asked 2×
- [Internal architecture of 8085](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3A8085-architecture) — Microprocessor, chapter 2, asked 3×
- [Short note: Register Transfer Language](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Ashort-note-rtl) — Microprocessor, chapter 1
- [8086 assembly language operators](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3A8086-operators) — Microprocessor, chapter 3, asked 3×

## Related in other subjects

- [General register organization in CPU](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Acpu-register-org) — Computer Organization and Architecture, chapter 2
- [PISO register with 1010 data](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Apiso-1010-data) — Digital Logic, chapter 7