---
title: "BIU and EU of 8086"
subject: "Microprocessor"
chapter: 3
key: "semester_4/microprocessor:8086-biu-vs-eu"
source: https://www.bctengineer.com/q/semester_4/microprocessor/8086-biu-vs-eu
site: BCT Engineering
---

# BIU and EU of 8086

Microprocessor · Chapter 3: Programming with 8086 Microprocessor

- Asked in: 2073 Magh, 4 marks
- Video: [Architecture of 8086 Microprocessor: Detailed Block Diagram and Data Flow Model 8086](https://www.youtube.com/watch?v=Uuxa90Xl4Rs) — Engineering Funda
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_4/microprocessor/8086-biu-vs-eu
- Whole chapter: https://www.bctengineer.com/md/semester_4/microprocessor/chapter-3

## Question

Discuss and differentiate between Bus Interface Unit (BIU) and Execution Unit (EU) of 8086 Microprocessor.

## Short answer

The BIU handles all external bus operations: it fetches instructions into a 6-byte queue, generates 20-bit addresses, and contains segment registers and IP. The EU decodes and executes instructions from the queue, contains general registers, ALU, flags, and control unit. They operate concurrently via pipelining.

## Answer

The 8086 is internally divided into the **Bus Interface Unit (BIU)** and the **Execution Unit (EU)**, which operate concurrently; this overlap of fetch and execute is called pipelining.

**BIU:** interfaces the processor with memory and I/O. It generates the 20-bit physical address (segment × 10H + offset), fetches instruction bytes into the 6-byte instruction queue, reads/writes operands and controls the buses. It contains segment registers (CS, DS, SS, ES), IP, the address adder, the queue and bus control logic.

**EU:** decodes and executes instructions taken from the queue. It contains the general registers (AX, BX, CX, DX), pointer/index registers (SP, BP, SI, DI), the ALU, flag register and control unit. When it needs memory or I/O, it asks the BIU.

| Point | BIU | EU |
|---|---|---|
| Main function | Fetch instructions, access memory/I/O | Decode and execute instructions |
| Contains | Segment registers, IP, address adder, queue | General registers, ALU, flags, control unit |
| Bus access | Directly connected to buses | No direct bus connection |
| Address work | Forms 20-bit physical address | Supplies the offset (effective address) |
| Queue | Fills the 6-byte queue | Removes instructions from the queue |
| Idle condition | Waits when queue is full | Waits when queue is empty (e.g. after a jump) |

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. Which statement correctly splits the roles?
   A. BIU decodes and executes; EU fetches
   B. BIU fetches instructions and accesses memory/I/O; EU decodes and executes
   C. Both only execute
   D. EU forms the 20-bit address
   Answer: B. BIU handles the bus; EU decodes and executes from the queue. (Key point: Function)

2. Which unit is directly connected to the buses?
   A. EU
   B. BIU
   C. Both
   D. Neither
   Answer: B. The EU has no direct bus connection; it asks the BIU. (Key point: Bus access)

3. When does the EU wait?
   A. When the queue is full
   B. When the queue is empty, e.g. after a jump
   C. Never
   D. When flags are clear
   Answer: B. After a jump the queue is flushed, so the EU waits; the BIU waits when the queue is full. (Key point: Idle condition)

## Related in Microprocessor

- [Bus Interface Unit of 8086](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3A8086-bus-interface-unit) — Microprocessor, chapter 3
- [IVT in 8086 and ISR execution sequence](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aivt-8086-isr-execution-sequence) — Microprocessor, chapter 5
- [Microprocessor based system and bus organization](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Amp-based-system-bus-organization) — Microprocessor, chapter 1, asked 5×

## Related in other subjects

- [How interrupts interface with microprocessor](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Ainterrupt-interface-microprocessor) — Embedded System, chapter 5
- [Input/output interface unit design factors](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aio-interface-unit-importance) — Instrumentation II, chapter 7
- [I/O bus and interface modules](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Aio-bus-interface-modules) — Computer Organization and Architecture, chapter 7
- [PCI bus; 8255 printer interface at 5500H](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Apci-printer-5500h) — Instrumentation II, chapter 2