---
title: "Hardware interrupts available in 8086"
subject: "Microprocessor"
chapter: 5
key: "semester_4/microprocessor:8086-hardware-interrupts"
source: https://www.bctengineer.com/q/semester_4/microprocessor/8086-hardware-interrupts
site: BCT Engineering
---

# Hardware interrupts available in 8086

Microprocessor · Chapter 5: Interrupt Operations

- Asked in: 2074 Bhadra, 3 marks
- Video: [Hardware Interrupts and Interrupt Priority in 8086 Microprocessor | Interrupt Controller](https://www.youtube.com/watch?v=qigLrccx3Rk) — Engineering Funda
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_4/microprocessor/8086-hardware-interrupts
- Whole chapter: https://www.bctengineer.com/md/semester_4/microprocessor/chapter-5

## Question

Discuss the different hardware interrupts available in 8086.

## Short answer

The 8086 has two hardware interrupt pins: NMI (non-maskable, edge-triggered, fixed type 2) and INTR (maskable by IF, level-triggered, type supplied externally). NMI has higher priority; INTR uses two INTA cycles and can be expanded with an 8259A.

## Answer

The 8086 has two hardware interrupt pins, **NMI** and **INTR**, and one acknowledgement output INTA'.

| Feature | NMI (pin 17) | INTR (pin 18) |
|---|---|---|
| Name | Non-maskable interrupt | Interrupt request |
| Trigger | Rising edge (must stay high for 2 clocks) | High level (sampled at end of instruction) |
| Maskable | No | Yes, by flag IF (CLI/STI) |
| Type number | Fixed, type 2 (vector at 00008H) | Supplied by external device/8259A on D7–D0 |
| INTA' cycles | Not generated | Two INTA' cycles |
| Priority | Higher | Lower |
| Use | Power failure, memory parity error | Ordinary I/O devices |

- When INTR is accepted, the 8086 pushes FLAGS, CS and IP, clears IF and TF, and gets the vector from the table at 4 × type.
- For many devices on one INTR pin, an 8259A programmable interrupt controller is used (up to 8 inputs, extendable by cascading).
- NMI is used for events that need immediate attention, while INTR handles normal devices under software control.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. Which are the two hardware interrupt pins of the 8086?
   A. NMI and INTR
   B. TRAP and INTR
   C. NMI and TRAP
   D. INTR and INTA'
   Answer: A. The 8086 has NMI and INTR; INTA' is the acknowledge output. (Key point: Pins)

2. How does the 8086 get the vector for NMI?
   A. The 8259A supplies the type number
   B. It is fixed at type 2, with the vector at 00008H
   C. It is read after two INTA' cycles
   D. It is type 0 at 00000H
   Answer: B. NMI is fixed at type 2 and needs no INTA' cycles. (Key point: NMI vector)

3. Which is true of INTR in the 8086?
   A. It is edge-triggered and cannot be masked
   B. It has higher priority than NMI
   C. It is maskable by IF and the type number comes in two INTA' cycles
   D. It uses a fixed vector
   Answer: C. INTR is level-triggered, maskable by IF, and the device/8259A provides the type on D7-D0. (Key point: INTR details)

## Related in Microprocessor

- [Hardware vs software interrupts](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Ahardware-vs-software-interrupts) — Microprocessor, chapter 5
- [Interrupts and handling with single INTR pin](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Ainterrupt-importance-single-intr) — Microprocessor, chapter 5
- [Interrupt processing in 8086](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Ainterrupt-processing-8086) — Microprocessor, chapter 5, asked 3×
- [Addressing modes of 8086](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3A8086-addressing-modes) — Microprocessor, chapter 3, asked 2×
- [ISR, IVT and type 0 to 4 interrupts](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aivt-ir-isr-type-0-to-4) — Microprocessor, chapter 5