--- title: "Address decoding with PROM decoder" subject: "Microprocessor" chapter: 4 key: "semester_4/microprocessor:address-decoding-prom" source: https://www.bctengineer.com/q/semester_4/microprocessor/address-decoding-prom site: BCT Engineering --- # Address decoding with PROM decoder Microprocessor · Chapter 4: Microprocessor System - Asked in: 2072 Asoj, 2+6 marks - Video: [Address decoding Circuit](https://www.youtube.com/watch?v=esqh_3qi-R4) — IOE-BCT - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_4/microprocessor/address-decoding-prom - Whole chapter: https://www.bctengineer.com/md/semester_4/microprocessor/chapter-4 ## Question What do you understand by address decoding? Explain with example how PROM decoder is used in memory address decoding. ## Short answer Address decoding generates a chip-select from higher address lines so only one device responds. A PROM can act as a programmable decoder: address lines select outputs programmed to assert the required chip-select. Example: 8085 with four 8K devices uses A15-A13 to select ROM1, ROM2, RAM1, RAM2. ## Answer **Address decoding** is the process of using the higher-order address lines (and control signals) to generate the chip-select signal of a memory or I/O device, so that only one device is active for a given address. The lower-order lines go directly to the device to select a location inside it. #### PROM as a decoder A **PROM** (programmable read-only memory) can be used as a programmable decoder. The address lines to be decoded are connected to the PROM's address inputs, and its data outputs are the chip-select signals (active low). The PROM contents are programmed so that, for each input combination, only the required output is 0. **Advantages:** any memory map, even one with irregular blocks, can be implemented by programming; it needs fewer chips than logic built from gates or a 74LS138; the map can be changed by reprogramming; and it is fast. #### Example 8085 system with four 8K devices: ROM1 (0000–1FFFH), ROM2 (2000–3FFFH), RAM1 (4000–5FFFH), RAM2 (6000–7FFFH). A15, A14, A13 go to PROM address inputs A2, A1, A0; outputs O0–O3 (active low) go to the CS' of the four chips. A12–A0 go to the chips directly. ```text A15 A14 A13 | O3 O2 O1 O0 | Selected 0 0 0 | 1 1 1 0 | ROM1 0000-1FFF 0 0 1 | 1 1 0 1 | ROM2 2000-3FFF 0 1 0 | 1 0 1 1 | RAM1 4000-5FFF 0 1 1 | 0 1 1 1 | RAM2 6000-7FFF 1 x x | 1 1 1 1 | none 8000-FFFF ``` ```text A15 -->[A2 O0]--> CS' ROM1 A14 -->[A1 PROM O1]--> CS' ROM2 A13 -->[A0 O2]--> CS' RAM1 O3 --> CS' RAM2 ``` For address 4A00H: A15A14A13 = 010, so O2 = 0 and only RAM1 is selected. The stored data (E, D, B, 7 in hex for the low nibble, and F for the unused rows) is written into the PROM once, when it is programmed. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What is the role of address decoding? A. To store the address in the chip B. To amplify the address signals C. To use higher-order lines to generate the chip select so only one device is active, with low-order lines selecting a location inside it D. To connect data lines to the chip Answer: C. Higher-order address lines make the chip select; lower-order lines go to the device to pick a location. (Key point: Purpose of decoding) 2. How is a PROM used as a decoder? A. The data lines of the CPU are the PROM inputs B. Address lines to be decoded go to the PROM address inputs, and its data outputs are the active-low chip selects C. The PROM stores the program for each device D. The PROM outputs are connected to the address bus Answer: B. The PROM is programmed so each input combination gives exactly the required chip select output as 0. (Key point: PROM as decoder) 3. In the PROM example, which chip is selected for address 4A00H? A. RAM1 (A15A14A13 = 010, so O2 = 0) B. ROM2 C. RAM2 D. No chip Answer: A. 4A00H has A15A14A13 = 010, so only output O2 goes low and RAM1 (4000-5FFF) is selected. (Key point: Example address 4A00H) 4. What is an advantage of a PROM decoder? A. It needs no programming B. It is only suitable for regular blocks C. It is slower than gates D. Any memory map, even irregular, can be implemented and changed by reprogramming Answer: D. Because contents are programmed, any map is possible with fewer chips than gate or 74LS138 logic. (Key point: PROM advantage) ## Related in Microprocessor - [Unique/non-unique decoding, memory mapped I/O](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aunique-nonunique-decoding-memory-mapped-io) — Microprocessor, chapter 4 - [Address decoding for input and output ports](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-input-output-port-block-decoder) — Microprocessor, chapter 4 - [Address decoding for two 8 KB RAM at C000H](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-two-8kb-ram-c000h) — Microprocessor, chapter 4 - [Address decoding for input port at 8050H](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-input-port-lda-8050h) — Microprocessor, chapter 4 - [Address decoding for 8 LEDs output port](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-output-port-8-leds) — Microprocessor, chapter 4 - [Interface two 4K x 8 ROM with 3:8 decoder](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-two-4k-rom-38-decoder) — Microprocessor, chapter 4 ## Related in other subjects - [Full vs partial address decoding for memory](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Afull-vs-partial-decoding) — Instrumentation II, chapter 2 - [Unique vs non-unique address decoding](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aunique-vs-nonunique-decoding) — Instrumentation II, chapter 2 - [Address sequencing for control memory](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Aaddress-sequencer) — Computer Organization and Architecture, chapter 3, asked 7× - [Address sequencing capabilities of control memory](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Aaddress-sequencing-capabilities) — Computer Organization and Architecture, chapter 3