---
title: "Bus organization and memory capacity"
subject: "Microprocessor"
chapter: 1
key: "semester_4/microprocessor:bus-organization-memory-capacity"
source: https://www.bctengineer.com/q/semester_4/microprocessor/bus-organization-memory-capacity
site: BCT Engineering
---

# Bus organization and memory capacity

Microprocessor · Chapter 1: Introduction to Microprocessor

- Asked in: 2072 Asoj, 1+5+2 marks
- Video: [System Buses : Address, Data and Control Bus Explained in Hindi l Microprocessor Series](https://www.youtube.com/watch?v=CNcv-vdkv4I) — 5 Minutes Engineering
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_4/microprocessor/bus-organization-memory-capacity
- Whole chapter: https://www.bctengineer.com/md/semester_4/microprocessor/chapter-1

## Question

What is Bus? Explain Bus organization of microprocessor with diagram. Calculate the memory handling capacity of the processor having address bus of 24 lines and data bus of 16 lines.

## Short answer

A microprocessor uses three buses: address (unidirectional, selects location), data (bidirectional, transfers data), and control (timing and direction signals). With a 24‑line address bus, 2^24 = 16 M locations are addressable; a 16‑bit data bus makes each location 2 bytes, giving a total capacity of 32 MB.

## Answer

#### Bus
A **bus** is a set of parallel lines that carries information (address, data, control signals) between the CPU, memory and I/O devices.

#### Bus organization

```text
 +-------+     +-----------+     +-----------+
 |  CPU  |     |  Memory   |     |   I/O     |
 |       |     | (ROM/RAM) |     |  (ports)  |
 +-+-+-+-+     +-+---+---+-+     +-+---+---+-+
   | | |         |   |   |         |   |   |
 ==+=+=+=========+===+===+=========+===+===+==  Address bus (n lines, CPU -> others)
   | |           |   |             |   |
 ==+=+===========+===+=============+===+======  Data bus (m lines, two way)
   |                 |                 |
 ==+=================+=================+======  Control bus (RD, WR, IO/M ...)
```

- **Address bus**: one-directional, from CPU to memory/I/O. It selects one location out of 2ⁿ.
- **Data bus**: bi-directional; moves data and instruction codes. Its width gives the word size.
- **Control bus**: signals like memory read/write, I/O read/write, interrupt, ready, hold, clock and reset that coordinate the transfers.

All devices share these common buses, and only the device selected by the address decoder responds.

#### Memory capacity
Address lines = 24, so the number of locations = 2²⁴ = 16,777,216 = 16 M locations.

Data bus = 16 lines. Assuming each location holds one data-bus-wide word, each location is 16 bits = 2 bytes.

```text
Total bits  = 2^24 x 16 = 268,435,456 bits
Total bytes = 16 M x 2  = 32 MB
```

**Answer: 16 M locations of 16 bits each = 32 MB.** (If memory is organised as 8-bit bytes, the processor can address 2²⁴ = 16 MB.)

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. How many locations can a 24-line address bus address?
   A. 24^2
   B. 2 x 24
   C. 2^24 = 16 M
   D. 2^16
   Answer: C. n address lines give 2^n locations; 2^24 = 16,777,216. (Key point: Locations from address lines)

2. With a 16-line data bus, what is the size of each location (assuming word-wide locations)?
   A. 8 bits
   B. 16 bits = 2 bytes
   C. 24 bits
   D. 32 bits
   Answer: B. Each location is as wide as the data bus: 16 bits = 2 bytes. (Key point: Bytes per location)

3. What is the memory capacity assuming word-wide locations?
   A. 16 MB
   B. 32 MB
   C. 48 MB
   D. 24 MB
   Answer: B. 16 M x 2 bytes = 32 MB. (If byte-organised, it would be 16 MB.) (Key point: Total capacity)

4. Which statement about the address bus direction is correct?
   A. It carries addresses from CPU to memory/I/O only
   B. It is bidirectional
   C. It carries addresses into the CPU
   D. It carries control signals
   Answer: A. The address bus is one-directional from the CPU. (Key point: Address bus direction)

## Related in Microprocessor

- [Microprocessor based system and bus organization](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Amp-based-system-bus-organization) — Microprocessor, chapter 1, asked 5×
- [Memory capacity from range and interfacing](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Amemory-range-capacity-interfacing) — Microprocessor, chapter 4
- [8085 ALP: compare two tables of 16-bit data](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aalp-8085-compare-tables-1ffffh) — Microprocessor, chapter 2
- [EI, DI, SIM, RIM and ISR address](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aei-di-sim-rim-vector-address) — Microprocessor, chapter 5
- [Unique/non-unique decoding, memory mapped I/O](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aunique-nonunique-decoding-memory-mapped-io) — Microprocessor, chapter 4
- [Address decoding with PROM decoder](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aaddress-decoding-prom) — Microprocessor, chapter 4

## Related in other subjects

- [Data bus and address bus width](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Abus-widths) — Computer Organization and Architecture, chapter 1, asked 2×
- [8051 data memory organization](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3A8051-data-memory-organization) — Embedded System, chapter 9
- [Address sequencing for control memory](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Aaddress-sequencer) — Computer Organization and Architecture, chapter 3, asked 7×
- [Performance balance of processor and memory](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Aperf-balance) — Computer Organization and Architecture, chapter 1