--- title: "Interfacing 2732 EPROM and 6116 RAM" subject: "Microprocessor" chapter: 4 key: "semester_4/microprocessor:decoder-74ls138-2732-6116" source: https://www.bctengineer.com/q/semester_4/microprocessor/decoder-74ls138-2732-6116 site: BCT Engineering --- # Interfacing 2732 EPROM and 6116 RAM Microprocessor · Chapter 4: Microprocessor System - Asked in: 2073 Bhadra, 8 marks - Video: [Memory interfacing in 8085 Microprocessor | Interface 16KB RAM & 4KB ROM with 8085 | MPMC BEC502](https://www.youtube.com/watch?v=AGtj9pPwDZY) — Techno Tutorials ( e-Learning) - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_4/microprocessor/decoder-74ls138-2732-6116 - Whole chapter: https://www.bctengineer.com/md/semester_4/microprocessor/chapter-4 ## Question Design an interfacing circuit for following problem. i) 74LS138: 3 to 8 Decoder ii) 2732 (4K*8): EP-ROM address range should begin at 0000H and additional 4K memory space should be available for future explanation iii) 6116 (2K*8): CMOS R/W memory ## Short answer EPROM 4K at 0000H–0FFFH, spare 4K at 1000H–1FFFH, RAM 2K at 2000H–27FFH. Decoder: 74LS138, C,B,A = A13,A12,A11, G1=+5V, G2A'=IO/M', G2B'=A15 OR A14. Y0' and Y1' ANDed to CE' of 2732, Y4' to CS' of 6116. A11–A0 to EPROM, A10–A0 to RAM, RD' to OE', WR' to WE' of RAM. ## Answer Chips: 2732 is a 4K×8 EPROM (A11–A0, pins CE' and OE'/Vpp). 6116 is a 2K×8 CMOS static RAM (A10–A0, pins CS', OE', WE'). #### Memory map (my choice) | Block | Device | Range | A15 A14 A13 A12 A11 | |---|---|---|---| | 1 | 2732 EPROM (4K) | 0000H – 0FFFH | 0 0 0 0 x | | 2 | Spare (future 4K) | 1000H – 1FFFH | 0 0 0 1 x | | 3 | 6116 RAM (2K) | 2000H – 27FFH | 0 0 1 0 0 | The EPROM starts at 0000H as required (the 8085 begins execution at 0000H after reset). The next 4K is kept free for future expansion. #### Decoder connections (74LS138) - C, B, A = A13, A12, A11. The EPROM covers 000 and 001 → Y0', Y1' (combined by an AND gate → CE' of 2732). - Future block: 010 and 011 → Y2', Y3' (left free, or ANDed and taken to a connector for a future 4K chip). - 6116: 100 → Y4' → CS'. - G1 = +5 V; G2A' = IO/M'; G2B' = output of an OR gate (A15 + A14), so A15 = A14 = 0 is needed. - A11–A0 to 2732; A10–A0 to 6116. - RD' → OE' of 2732 and 6116; WR' → WE' of 6116. ```text A13 ---- C \ A12 ---- B | 74LS138 Y0' --+ A11 ---- A / [AND]-- CE' 2732 (0000-0FFF) IO/M' -- G2A' Y1' --+ A15 --+ Y2' --+ [OR]-- G2B' +------ spare (1000-1FFF) A14 --+ Y3' --+ +5V ---- G1 Y4' ---------- CS' 6116 (2000-27FF) RD' -> OE' of both; WR' -> WE' of 6116 ``` The lower address byte is multiplexed with data on AD7–AD0, so a 74LS373 latch enabled by ALE is first used to separate A7–A0. A15–A8 are available directly. Signals marked with a prime (RD', WR', IO/M', CE', OE') are active low. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. Why are Y0' and Y1' combined by an AND gate for the 2732? A. The 2732 is 8K B. The 2732 needs a write pulse C. The 4K chip covers two 2K decoder blocks (0000-07FF and 0800-0FFF) D. To enable the RAM Answer: C. With select lines A13-A11 each output is a 2K block, so 4K needs two outputs combined. (Key point: EPROM select) 2. Which range is kept for the future 4K and which outputs does it use? A. 2000H-2FFFH; Y4' and Y5' B. 0800H-17FFH; Y1' and Y2' C. 0000H-0FFFH; Y0' and Y1' D. 1000H-1FFFH; Y2' and Y3' Answer: D. The 4K after 0000H-0FFFH is 1000H-1FFFH, patterns 010 and 011 (Y2', Y3'). (Key point: Spare block) 3. Where is the 6116 placed and which output selects it? A. 2000H-27FFH, Y4' (pattern 100) B. 2000H-2FFFH, Y5' C. 0800H-0FFFH, Y1' D. 1000H-17FFH, Y2' Answer: A. After the EPROM and spare 4K, the 2K RAM is at 2000H-27FFH (A13A12A11 = 100) on Y4'. (Key point: 6116 selection) 4. How many address lines does the 6116 use, and what are its control connections? A. 12 lines; only OE' B. 11 lines (A10-A0); RD' to OE' only, no write C. 11 lines (A10-A0); RD' to OE' and WR' to WE' D. 13 lines; only CS' Answer: C. 2K = 2^11 locations so A10-A0 are used, and as RAM it needs both OE' (RD') and WE' (WR'). (Key point: 6116 pins) ## Related in Microprocessor - [74LS138 interfacing of ROM, RAM, EPROM](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-74ls138-rom-ram-eprom) — Microprocessor, chapter 4 - [Interface two 4K x 8 ROM with 3:8 decoder](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-two-4k-rom-38-decoder) — Microprocessor, chapter 4 - [Memory capacity from range and interfacing](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Amemory-range-capacity-interfacing) — Microprocessor, chapter 4 - [Interface 4 KB EPROM and two 2 KB RAM](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Ainterface-4kb-eprom-two-2kb-ram) — Microprocessor, chapter 4 ## Related in other subjects - [8086 RAM/EPROM interfacing with reset address](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Arom-ram-8086-fffffh) — Instrumentation II, chapter 1 - [DMA concept; ROM/RAM interface at 4000H](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Adma-memory-interface-4000h) — Instrumentation II, chapter 1