--- title: "74LS138 interfacing of ROM, RAM, EPROM" subject: "Microprocessor" chapter: 4 key: "semester_4/microprocessor:decoder-74ls138-rom-ram-eprom" source: https://www.bctengineer.com/q/semester_4/microprocessor/decoder-74ls138-rom-ram-eprom site: BCT Engineering --- # 74LS138 interfacing of ROM, RAM, EPROM Microprocessor · Chapter 4: Microprocessor System - Asked in: 2073 Magh, 8 marks - Video: [Microprocessor 8085 - Memory Address decoding using 74LS138](https://www.youtube.com/watch?v=tO5HGTrEMeg) — Nissamuddeen Kunnath - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_4/microprocessor/decoder-74ls138-rom-ram-eprom - Whole chapter: https://www.bctengineer.com/md/semester_4/microprocessor/chapter-4 ## Question With a neat diagram explain the interfacing circuit using a 3:8 decoder (74LS138) needed to connect the following memory units to the 8085 microprocessor consecutively starting from memory location A000H. 2K×8 ROM chip 2K×8 RAM chip 4K×8 EPROM chip ## Short answer ROM 2K at A000H–A7FFH, RAM 2K at A800H–AFFFH, EPROM 4K at B000H–BFFFH. Decoder: 74LS138 with C,B,A = A13,A12,A11; G1=A15, G2A'=A14, G2B'=IO/M'. Y4' selects ROM, Y5' selects RAM, Y6' and Y7' ANDed select EPROM. RD' to OE' all, WR' to WE' RAM, A10–A0 to 2K chips, A11–A0 to EPROM. ## Answer The decoder must give 2K-block selection, so the select inputs are A13, A12, A11. Chip sizes: 2K×8 needs 11 address lines (A10–A0); 4K×8 needs 12 (A11–A0). #### Address map (starting at A000H, consecutive) | Device | Size | Range | A15 A14 A13 A12 A11 | |---|---|---|---| | ROM | 2K | A000H – A7FFH | 1 0 1 0 0 | | RAM | 2K | A800H – AFFFH | 1 0 1 0 1 | | EPROM | 4K | B000H – BFFFH | 1 0 1 1 x | #### Decoder connections (74LS138) - C, B, A = A13, A12, A11. ROM: 100 → Y4'. RAM: 101 → Y5'. EPROM: 11x covers 110 and 111 → Y6' and Y7'. - G1 = A15 (must be 1); G2A' = A14 (must be 0); G2B' = IO/M' (must be 0). - Y4' → CS' of ROM; Y5' → CS' of RAM. - Y6' and Y7' are combined by a 2-input AND gate (output low when either is low) → CE' of the 4K EPROM. - ROM, RAM and EPROM address pins: A10–A0 (2K chips) and A11–A0 (EPROM). - RD' → OE' of all three; WR' → WE' of the RAM only. ```text A13 -- C \ A12 -- B | 74LS138 +------+ A11 -- A / Y4' ------- |ROM 2K| A000-A7FF A15 -- G1 Y5' ------- |RAM 2K| A800-AFFF A14 -- G2A' +------+ IO/M' - G2B' Y6' --+ [AND]---- |EPROM 4K| B000-BFFF Y7' --+ A10-A0 -> ROM, RAM; A11-A0 -> EPROM RD' -> OE' (all); WR' -> WE' (RAM); D7-D0 common ``` The lower address byte is multiplexed with data on AD7–AD0, so a 74LS373 latch enabled by ALE is first used to separate A7–A0. A15–A8 are available directly. Signals marked with a prime (RD', WR', IO/M', CE', OE') are active low. Only one chip select is low at a time, so only one device drives the data bus. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. Why are A13, A12, A11 used as the decoder select inputs? A. The decoder needs A15-A13 always B. The smallest chip is 2K, so the decoder must resolve 2K blocks C. The EPROM is 8K D. Because IO/M' is not used Answer: B. 2K blocks are distinguished by A13-A11 (A10-A0 address inside a 2K chip). (Key point: Select lines) 2. What is the address range of the 2K RAM following the 2K ROM at A000H? A. A800H-AFFFH B. A000H-A7FFH C. B000H-B7FFH D. A800H-BFFFH Answer: A. ROM covers A000H-A7FFH, and the next 2K (A800H-AFFFH, pattern 10101) is the RAM on Y5'. (Key point: RAM range) 3. Why are Y6' and Y7' combined with an AND gate for the 4K EPROM? A. To select the RAM too B. To produce the write signal C. To increase the drive D. A 4K chip covers two 2K blocks, so either output going low must enable it Answer: D. B000H-BFFFH spans patterns 110 and 111, so the AND output is low when either Y6' or Y7' is low. (Key point: EPROM select) 4. Which chip gets WR' on its WE' pin? A. ROM, RAM and EPROM B. Only the RAM C. Only the EPROM D. Only the ROM Answer: B. Only the RAM can be written; RD' goes to OE' of all three. (Key point: Write signal) ## Related in Microprocessor - [Interfacing 2732 EPROM and 6116 RAM](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-74ls138-2732-6116) — Microprocessor, chapter 4 - [Interface two 4K x 8 ROM with 3:8 decoder](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-two-4k-rom-38-decoder) — Microprocessor, chapter 4 - [Interface 4 KB EPROM and two 2 KB RAM](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Ainterface-4kb-eprom-two-2kb-ram) — Microprocessor, chapter 4 - [Memory capacity from range and interfacing](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Amemory-range-capacity-interfacing) — Microprocessor, chapter 4 ## Related in other subjects - [8086 RAM/EPROM interfacing with reset address](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Arom-ram-8086-fffffh) — Instrumentation II, chapter 1 - [Interfacing: 512-byte RAM with 8085](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Arag-ram-512-interface) — Instrumentation II, chapter 2 - [DMA concept; ROM/RAM interface at 4000H](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Adma-memory-interface-4000h) — Instrumentation II, chapter 1 - [Compose 1K x 8 ROMs into 4K x 8 ROM](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Acompose-4kx8-from-1kx8) — Embedded System, chapter 4, asked 2×