--- title: "Address decoding for input and output ports" subject: "Microprocessor" chapter: 4 key: "semester_4/microprocessor:decoder-input-output-port-block-decoder" source: https://www.bctengineer.com/q/semester_4/microprocessor/decoder-input-output-port-block-decoder site: BCT Engineering --- # Address decoding for input and output ports Microprocessor · Chapter 4: Microprocessor System - Asked in: 2070 Magh, 8 marks - Video: [Interfacing of Input and output Devices with 8085 | MPMC | Input / Output interfacing | PYQ | 22-23](https://www.youtube.com/watch?v=y56h3f6jYXg) — Techno Tutorials ( e-Learning) - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_4/microprocessor/decoder-input-output-port-block-decoder - Whole chapter: https://www.bctengineer.com/md/semester_4/microprocessor/chapter-4 ## Question Design the address decoding interface of an input port and output port for 8085 at 81 H and 82 H address. Use block decoder. ## Short answer Use a 74LS138 block decoder with A2-A0 selecting outputs and A7 plus A6-A3 enabling it, gated by IO/M. Y1 and Y2 select ports 81H and 82H; combine with RD for input buffer enable and WR for output latch clock. IN 81H reads, OUT 82H writes. ## Answer Peripheral (isolated) I/O is used, so the port address is the 8-bit address on A7–A0 and IO/M' must be high. A 74LS138 (3:8 decoder) is used as the block decoder: it decodes the block 80H–87H, and the two outputs Y1' and Y2' give the ports 81H and 82H. The lower address byte is multiplexed with data on AD7–AD0, so a 74LS373 latch enabled by ALE is first used to separate A7–A0. A15–A8 are available directly. Signals marked with a prime (RD', WR', IO/M', CE', OE') are active low. #### Address decoding | Port | Address | A7 A6 A5 A4 A3 | A2 A1 A0 | Output | |---|---|---|---|---| | Input port | 81H | 1 0 0 0 0 | 0 0 1 | Y1' | | Output port | 82H | 1 0 0 0 0 | 0 1 0 | Y2' | - A2, A1, A0 are connected to the select inputs C, B, A of the decoder. - A7 is connected to enable G1 (must be 1). - A6, A5, A4, A3 go through a 4-input OR gate to enable G2A' (it is 0 only when all four are 0). - IO/M' goes through an inverter to G2B', so the decoder is enabled only in an I/O cycle (IO/M' = 1). #### Circuit ```text A2 --- C \ A1 --- B | 74LS138 A0 --- A / A7 ---------- G1 A6..A3 -[OR4]- G2A' IO/M' -[NOT]-- G2B' Y1' --+--[OR]-- to 74LS244 | ^ enable (G') | RD' Y2' --[NOR]-- LE of 74LS373 ^ WR' Input : 74LS244 buffer, D0-D7 from device -> AD7-AD0 Output: 74LS373 latch, AD7-AD0 -> D0-D7 to device ``` #### Working - **IN 81H:** the CPU puts 81H on A7–A0 and IO/M' = 1. Y1' goes low. When RD' also goes low, the OR gate output is low and enables the 3-state buffer, so the device data reaches the data bus. - **OUT 82H:** Y2' goes low. When WR' goes low the NOR gate output goes high; the latch is transparent and takes the data. When WR' returns high the output falls and the latch holds the data for the output device. Other outputs of the decoder (Y0', Y3'–Y7') remain free for more ports in the block 80H–87H. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. Which block does the 74LS138 decode in this design, and why are 81H and 82H inside it? A. 00H-07H B. 80H-87H, since A7 = 1 and A6-A3 = 0 are fixed and A2-A0 select within the block C. 80H-FFH D. 81H-82H only Answer: B. A7 = 1 and A6-A3 = 0 fix the block 80H-87H; A2-A0 pick Y1' for 81H and Y2' for 82H. (Key point: Block decoded) 2. Why is a 74LS373 latch enabled by ALE used first? A. To increase drive current of the data bus B. To store the output data C. To separate the multiplexed low address byte A7-A0 from the data lines D. To generate IO/M' Answer: C. AD7-AD0 carry the low address then data, so the latch holds A7-A0 while data uses the lines. (Key point: Why latch and ALE) 3. Why does IO/M' go through an inverter to G2B'? A. So the decoder is enabled only in I/O cycles B. So memory cycles enable it C. So RD' is inverted D. So A7 is inverted Answer: A. IO/M' is 1 in I/O cycles; the inverter makes G2B' = 0 only then, so memory addresses never select the ports. (Key point: Enable by IO/M') 4. In OUT 82H, how does the output latch capture the data? A. Y2' goes low and RD' enables the buffer B. Y1' goes low and WR' enables the buffer C. Latch is enabled by ALE D. Y2' goes low, WR' low makes the NOR output high so the latch is transparent, then holds the data when WR' returns high Answer: D. The NOR of Y2' and WR' opens the latch during the write and it holds data when WR' goes high. (Key point: Output port working) ## Related in Microprocessor - [Address decoding for 8 LEDs output port](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-output-port-8-leds) — Microprocessor, chapter 4 - [Address decoding for input port at 8050H](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-input-port-lda-8050h) — Microprocessor, chapter 4 - [Address decoding with PROM decoder](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aaddress-decoding-prom) — Microprocessor, chapter 4 - [Address decoding for two 8 KB RAM at C000H](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-two-8kb-ram-c000h) — Microprocessor, chapter 4 - [Interface two 4K x 8 ROM with 3:8 decoder](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-two-4k-rom-38-decoder) — Microprocessor, chapter 4 ## Related in other subjects - [Input/output interface unit design factors](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aio-interface-unit-importance) — Instrumentation II, chapter 7 - [Memory-mapped I/O design for 8085](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Amemmapped-io-design-1000h) — Instrumentation II, chapter 2 - [8-channel ADC interface with 8255 and 8085](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aadc8-8255-problem) — Instrumentation II, chapter 4 - [8255 port addresses from decoder figure](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Appi-port-addresses-decoder-fig) — Instrumentation II, chapter 2