---
title: "Address decoding for input port at 8050H"
subject: "Microprocessor"
chapter: 4
key: "semester_4/microprocessor:decoder-input-port-lda-8050h"
source: https://www.bctengineer.com/q/semester_4/microprocessor/decoder-input-port-lda-8050h
site: BCT Engineering
---

# Address decoding for input port at 8050H

Microprocessor · Chapter 4: Microprocessor System

- Asked in: 2069 Poush, 5 marks
- Video: [Address Decoding](https://www.youtube.com/watch?v=nOMyv79cqKQ) — AAkrit Subedi
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_4/microprocessor/decoder-input-port-lda-8050h
- Whole chapter: https://www.bctengineer.com/md/semester_4/microprocessor/chapter-4

## Question

Design an address decoding circuit for an input port interfaced at address 8050H such that LDA 8050 instruction can be used to read from that port.

## Short answer

This is memory-mapped I/O; decode full 16-bit address 8050H and IO/M'=0 using a 74LS138. Connect A6, A5, A4 to C, B, A (pattern 101 gives Y5'), A15 to G1, A14–A7 ORed to G2A', A3–A0 and IO/M' ORed to G2B'. Y5' combined with RD' enables a 74LS244 buffer to place port data on the data bus.

## Answer

LDA 8050H is a memory read instruction, so the port is **memory-mapped**: the CPU gives IO/M' = 0, the full 16-bit address 8050H and then RD'. The circuit must therefore decode all 16 address lines and IO/M' (no foldback).

The lower address byte is multiplexed with data on AD7–AD0, so a 74LS373 latch enabled by ALE is first used to separate A7–A0. A15–A8 are available directly. Signals marked with a prime (RD', WR', IO/M', CE', OE') are active low.

#### Address pattern

```text
8050H = 1000 0000 0101 0000
        A15            A6 A4 = 1, all other lines = 0
```

- Lines that must be 1: A15, A6, A4.
- Lines that must be 0: A14–A7, A5, A3–A0, and IO/M'.

#### Design using a 74LS138

- Select inputs: C = A6, B = A5, A = A4 → pattern 1 0 1 → output **Y5'**.
- Enable G1 = A15 (must be 1).
- Enable G2A' = OR of (A14, A13, A12, A11, A10, A9, A8, A7). It is 0 only if all eight lines are 0.
- Enable G2B' = OR of (A3, A2, A1, A0, IO/M'). It is 0 only if these lines are all 0.

```text
 A6 --- C \
 A5 --- B  | 74LS138
 A4 --- A /
 A15 ------------ G1
 A14..A7 -[OR8]-- G2A'
 A3..A0,IO/M' -[OR5]- G2B'
                  Y5' --[OR]-- G' of 74LS244
                           ^   (input port buffer)
                          RD'
 Port data lines -> 74LS244 -> D7..D0 (AD7..AD0)
```

#### Working

When the CPU executes LDA 8050H, all conditions are met only for address 8050H, so Y5' becomes low. With RD' low the OR gate enables the 74LS244 buffer; the port data goes on the data bus and the 8085 loads it into the accumulator. For every other address Y5' stays high and the buffer is in high impedance.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. Why must the port at 8050H be memory-mapped?
   A. LDA is an I/O instruction using IO/M' = 1
   B. LDA is a memory read instruction, so IO/M' = 0 and all 16 address lines are decoded
   C. IN is used
   D. It uses only 8 address lines
   Answer: B. LDA 8050H generates a memory read cycle with a 16-bit address, so the port must appear in the memory map. (Key point: Memory mapped)

2. Which address lines must be 1 for 8050H = 1000 0000 0101 0000?
   A. A15 and A5
   B. A14, A6 and A4
   C. A15, A5 and A3
   D. A15, A6 and A4
   Answer: D. Bits set in 8050H are bit 15, bit 6 and bit 4, so A15, A6 and A4 are 1 and all other lines are 0. (Key point: Lines at logic 1)

3. With C = A6, B = A5, A = A4, which output is active for 8050H?
   A. Y5' (pattern 101)
   B. Y3'
   C. Y6'
   D. Y1'
   Answer: A. A6 A5 A4 = 1 0 1 selects Y5'. (Key point: Decoder output)

4. How does the data reach the accumulator when LDA 8050H executes?
   A. WR' low enables the buffer
   B. Y5' low and RD' low enable the 74LS244 buffer, putting port data on the data bus
   C. The 74LS373 latch is enabled
   D. IO/M' = 1 opens the buffer
   Answer: B. Y5' is low only for 8050H; with RD' low the buffer is enabled and the data goes to the bus and then into A. (Key point: Read working)

## Related in Microprocessor

- [Address decoding for input and output ports](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-input-output-port-block-decoder) — Microprocessor, chapter 4
- [Address decoding for 8 LEDs output port](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-output-port-8-leds) — Microprocessor, chapter 4
- [Address decoding with PROM decoder](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aaddress-decoding-prom) — Microprocessor, chapter 4
- [Address decoding for two 8 KB RAM at C000H](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-two-8kb-ram-c000h) — Microprocessor, chapter 4
- [Machine cycles involved in LDA](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Amachine-cycles-lda) — Microprocessor, chapter 2, asked 2×
- [Timing diagram of STA 8050H](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Atiming-sta-8050h) — Microprocessor, chapter 2

## Related in other subjects

- [Read switches at port 1, show on port 2](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3A8051-switch-port1-led-port2) — Embedded System, chapter 9, asked 2×
- [Unique vs non-unique address decoding](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aunique-vs-nonunique-decoding) — Instrumentation II, chapter 2
- [Full vs partial address decoding for memory](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Afull-vs-partial-decoding) — Instrumentation II, chapter 2
- [Instruction fields and address formats for X=(E+F)*(G+H)](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Acode-fields-e-f-g-h) — Computer Organization and Architecture, chapter 2