--- title: "Address decoding for 8 LEDs output port" subject: "Microprocessor" chapter: 4 key: "semester_4/microprocessor:decoder-output-port-8-leds" source: https://www.bctengineer.com/q/semester_4/microprocessor/decoder-output-port-8-leds site: BCT Engineering --- # Address decoding for 8 LEDs output port Microprocessor · Chapter 4: Microprocessor System - Asked in: 2075 Baisakh, 5 marks - Video: [Interfacing of Input and output Devices with 8085 | MPMC | Input / Output interfacing | PYQ | 22-23](https://www.youtube.com/watch?v=y56h3f6jYXg) — Techno Tutorials ( e-Learning) - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_4/microprocessor/decoder-output-port-8-leds - Whole chapter: https://www.bctengineer.com/md/semester_4/microprocessor/chapter-4 ## Question Design the address decoding interface of an output port consisting of 8 LEDs with port address ABH. ## Short answer For an 8085 output port at ABH, decode A7-A0 with inverters and an 8-input NAND so SEL is active only for ABH. Use a 74LS374 latch enabled by SEL and IOW to drive eight LEDs through resistors. Program: MVI A,0FFH; OUT 0ABH. ## Answer **Assumptions:** 8085 system with I/O-mapped I/O (an 8086 system is the same, with M/IO' = 0). Port address **ABH** = 1010 1011 B, decoded uniquely using all 8 address lines A7–A0. An 8-bit latch **74LS374** (octal D flip-flop; a 74LS373 transparent latch can also be used) holds the data, and 8 LEDs with current-limiting resistors are connected to its outputs. **Decoding logic** - A7 A6 A5 A4 A3 A2 A1 A0 = 1 0 1 0 1 0 1 1. - Lines that must be 0 (A6, A4, A2) pass through inverters; an 8-input NAND gives **SEL' = 0** only for address ABH. - The write pulse **IOW'** = WR' OR (NOT IO/M') is formed. IO/M' is 1 for I/O, so it is inverted first; IOW' is then low only for an I/O write. - The latch is enabled when both are active. With a positive-edge latch (74LS374) the clock is CLK = SEL' OR IOW'; the data is latched when IOW' returns high. With a transparent latch (74LS373), G = SEL AND IOW (active high). ```text A7 ---------------------------+ A6 --o>o---------------------+| A5 ---------------------------+| A4 --o>o---------------------+ |--[8-input NAND]--SEL'--+ A3 ---------------------------+| | A2 --o>o---------------------+ | [OR]-> CLK A1 ---------------------------+| | A0 ---------------------------+ IOW' --+ (WR' + NOT IO/M') D0-D7 ---------> [74LS374 latch] -> Q0-Q7 -> 330 ohm -> LED -> GND (OE' = 0) ``` An LED turns ON for logic 1 (use a driver such as 74LS244/ULN2803 if the latch cannot supply the LED current directly). **Address check** | Line | A7 | A6 | A5 | A4 | A3 | A2 | A1 | A0 | |---|---|---|---|---|---|---|---|---| | Required level | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | | Applied to NAND | A7 | A6' | A5 | A4' | A3 | A2' | A1 | A0 | Only the address ABH makes all NAND inputs 1, so SEL' = 0 for ABH alone (unique decoding). **Program to turn on all LEDs / alternate LEDs** ```asm MVI A,0FFH ; all LEDs ON OUT 0ABH ; send to port ABH MVI A,55H ; alternate LEDs ON OUT 0ABH HLT ``` 8086 version: `MOV AL,0FFH` then `OUT 0ABH,AL`. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. For port address ABH (1010 1011), which address lines are inverted before the 8-input NAND? A. A7, A5, A3, A1, A0 B. A7, A6, A5, A4 C. A6, A4, A2 D. None Answer: C. Lines that must be 0 (A6, A4, A2) pass through inverters so all NAND inputs are 1 only for ABH. (Key point: Inverted lines) 2. Why is this decoding unique? A. Only A7 is decoded B. All eight lines A7-A0 are used, so only ABH makes SEL' low C. IO/M' is ignored D. A 3:8 decoder is used Answer: B. Using all 8 address lines means exactly one address (ABH) gives SEL' = 0. (Key point: Unique decoding) 3. When is IOW' low? A. During any memory read B. During any I/O read C. Whenever ALE is high D. Only for an I/O write, when WR' is low and IO/M' is high Answer: D. IOW' = WR' OR (NOT IO/M'), which is low only when WR' = 0 and IO/M' = 1. (Key point: Write pulse IOW') 4. Which code lights alternate LEDs on the port? A. MVI A,55H then OUT 0ABH B. MVI A,0FFH then OUT 0ABH C. MVI A,00H then OUT 0ABH D. MVI A,55H then STA 0ABH Answer: A. 55H = 0101 0101 turns every second LED on; the data is sent with OUT to the I/O port ABH. (Key point: LED program) ## Related in Microprocessor - [Address decoding for input and output ports](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-input-output-port-block-decoder) — Microprocessor, chapter 4 - [Address decoding for input port at 8050H](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-input-port-lda-8050h) — Microprocessor, chapter 4 - [Address decoding for two 8 KB RAM at C000H](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-two-8kb-ram-c000h) — Microprocessor, chapter 4 - [Address decoding with PROM decoder](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aaddress-decoding-prom) — Microprocessor, chapter 4 - [Interface two 8K x 8 ROM at 4000H](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-two-8k-rom-4000h) — Microprocessor, chapter 4 - [Unique/non-unique decoding, memory mapped I/O](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aunique-nonunique-decoding-memory-mapped-io) — Microprocessor, chapter 4 ## Related in other subjects - [Blink 8 LEDs at port 2](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3A8051-blink-leds-port2) — Embedded System, chapter 9, asked 2× - [ADC at 80H with 8255A: display on port B LEDs](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aadc-8255-80h-leds) — Instrumentation II, chapter 2 - [Input/output interface unit design factors](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aio-interface-unit-importance) — Instrumentation II, chapter 7 - [Unique vs non-unique address decoding](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aunique-vs-nonunique-decoding) — Instrumentation II, chapter 2