--- title: "Interface two 4K x 8 ROM with 3:8 decoder" subject: "Microprocessor" chapter: 4 key: "semester_4/microprocessor:decoder-two-4k-rom-38-decoder" source: https://www.bctengineer.com/q/semester_4/microprocessor/decoder-two-4k-rom-38-decoder site: BCT Engineering --- # Interface two 4K x 8 ROM with 3:8 decoder Microprocessor · Chapter 4: Microprocessor System - Asked in: 2069 Bhadra, 8 marks - Video: [Interface 4k*8 ram, 4k * 8 rom, 8k * 8 ram with starting address 1000H | Microprocessor](https://www.youtube.com/watch?v=y_jt6E12kWQ) — SparkDiary - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_4/microprocessor/decoder-two-4k-rom-38-decoder - Whole chapter: https://www.bctengineer.com/md/semester_4/microprocessor/chapter-4 ## Question Interface two 4K×8 ROM with 3:8 decoder at the address of your choice. Show the address map for each ROM and explain your circuit. ## Short answer Place ROM1 at 0000H–0FFFH and ROM2 at 1000H–1FFFH. Each 4KB ROM needs A11–A0. Use 74LS138: C,B,A = A14,A13,A12, G2A'=A15, G2B'=IO/M', G1=+5V. Y0' enables ROM1, Y1' enables ROM2. A11–A0 connect to address lines, RD' to OE', data to D7–D0. ## Answer A 4K×8 ROM needs 12 address lines (A11–A0). I place ROM 1 at 0000H (the reset address, where the monitor program normally starts) and ROM 2 immediately after it. #### Address map | Chip | A15 A14 A13 A12 | A11–A0 | Range | |---|---|---|---| | ROM 1 | 0 0 0 0 | 000…0 to 111…1 | 0000H – 0FFFH | | ROM 2 | 0 0 0 1 | 000…0 to 111…1 | 1000H – 1FFFH | #### Circuit (74LS138) - Select inputs C, B, A = A14, A13, A12. Pattern 000 → Y0' (ROM 1); 001 → Y1' (ROM 2). - A15 must be 0 for both ROMs: connect A15 to G2A'. - IO/M' to G2B' (must be 0 for memory access). G1 = +5 V. - Y0' → CE' of ROM 1; Y1' → CE' of ROM 2. - A11–A0 go to both ROMs; RD' to OE' of both ROMs; D7–D0 from both ROMs to the data bus. ```text A14 --- C \ A13 --- B | 74LS138 +-------+ A12 --- A / Y0' -------- |CE' R1 | 0000-0FFF A15 --- G2A' Y1' ---+ +-------+ IO/M' - G2B' | +-------+ +5V --- G1 +-----|CE' R2 | 1000-1FFF +-------+ A11-A0 -> A11-A0 of both ROMs RD' -> OE' of both ROMs; D7-D0 <- ROM data ``` #### Explanation - When the 8085 reads an address in 0000H–0FFFH, A15–A12 = 0000, so Y0' goes low and only ROM 1 is enabled. A11–A0 select the byte in the chip, and RD' makes the chip put it on the data bus. - For 1000H–1FFFH, A15–A12 = 0001 and Y1' enables ROM 2. - Outputs Y2'–Y7' (2000H–7FFFH) are unused and can be used for more memory later. A15 = 1 disables the decoder, so the upper half of memory is free. - Only one ROM is enabled at a time, so there is no bus conflict. The lower address byte is multiplexed with data on AD7–AD0, so a 74LS373 latch enabled by ALE is first used to separate A7–A0. A15–A8 are available directly. Signals marked with a prime (RD', WR', IO/M', CE', OE') are active low. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. How many address lines does a 4K x 8 ROM need? A. 13 (A12-A0) B. 12 (A11-A0) C. 11 (A10-A0) D. 10 (A9-A0) Answer: B. 4K = 4096 = 2^12 locations, so 12 lines A11-A0 go to the chip. (Key point: Address lines for 4K) 2. Which lines drive C, B, A, and which output selects ROM 2 (1000H)? A. A15,A14,A13; Y1' B. A15,A14,A13; Y2' C. A14,A13,A12; Y1' D. A14,A13,A12; Y2' Answer: C. For 4K blocks the select inputs are A14,A13,A12; pattern 001 gives Y1' for 1000H-1FFFH. (Key point: Select inputs) 3. What happens when A15 is connected to G2A'? A. The decoder works only when A15 = 0; with A15 = 1 it is disabled, so the upper half is free B. The decoder works only when A15 = 1 C. The ROMs are always enabled D. A15 selects between ROM 1 and ROM 2 Answer: A. G2A' must be 0 to enable the decoder, so only addresses with A15 = 0 select a ROM. (Key point: A15 on G2A') 4. Why is the first ROM placed at 0000H? A. Memory cannot start elsewhere B. RAM must be at 0000H C. The decoder needs it D. The 8085 starts at 0000H after reset, so the monitor program must be in non-volatile ROM there Answer: D. After reset the 8085 fetches from 0000H, so the start-up program has to be in ROM at that address. (Key point: Why start at 0000H) ## Related in Microprocessor - [Interface two 8K x 8 ROM at 4000H](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-two-8k-rom-4000h) — Microprocessor, chapter 4 - [Address decoding with PROM decoder](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aaddress-decoding-prom) — Microprocessor, chapter 4 - [Address decoding for two 8 KB RAM at C000H](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-two-8kb-ram-c000h) — Microprocessor, chapter 4 - [74LS138 interfacing of ROM, RAM, EPROM](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-74ls138-rom-ram-eprom) — Microprocessor, chapter 4 - [Interface 4 KB EPROM and two 2 KB RAM](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Ainterface-4kb-eprom-two-2kb-ram) — Microprocessor, chapter 4 - [Address decoding for input and output ports](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-input-output-port-block-decoder) — Microprocessor, chapter 4 ## Related in other subjects - [Compose 1K x 8 ROMs into 4K x 8 ROM](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Acompose-4kx8-from-1kx8) — Embedded System, chapter 4, asked 2× - [Compose 4K x 16 ROM using 1K x 8](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Acompose-4kx16-from-1kx8) — Embedded System, chapter 4 - [DMA concept; ROM/RAM interface at 4000H](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Adma-memory-interface-4000h) — Instrumentation II, chapter 1 - [Interface circuit with 2 RAMs and 2 ROMs](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Ainterface-circuit-16bit-ram-rom) — Embedded System, chapter 5