---
title: "Interface two 8K x 8 ROM at 4000H"
subject: "Microprocessor"
chapter: 4
key: "semester_4/microprocessor:decoder-two-8k-rom-4000h"
source: https://www.bctengineer.com/q/semester_4/microprocessor/decoder-two-8k-rom-4000h
site: BCT Engineering
---

# Interface two 8K x 8 ROM at 4000H

Microprocessor · Chapter 4: Microprocessor System

- Asked in: 2074 Bhadra, 5 marks
- Video: [Interface 1Kbyte RAM starting from 4000H & 8Kbyte ROM starting 0000H & 8Kbyte ROM starting E000H](https://www.youtube.com/watch?v=eXkGo87OtOU) — Jay Explains
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_4/microprocessor/decoder-two-8k-rom-4000h
- Whole chapter: https://www.bctengineer.com/md/semester_4/microprocessor/chapter-4

## Question

Design an address decoding circuit to interface two 8k*8 ROM chips at address starting at 4000H.

## Short answer

Each 8KB ROM uses A12–A0; A15–A13 select chips. Decoder: 74LS138 with C,B,A = A15,A14,A13, G1=+5V, G2B'=GND, G2A'=IO/M'. Y2' enables ROM1 (4000H–5FFFH), Y3' enables ROM2 (6000H–7FFFH). RD' drives OE', A12–A0 connect to address lines, and data lines to D7–D0.

## Answer

An 8K×8 ROM has 8192 = 2¹³ locations, so it needs 13 address lines (A12–A0). The remaining lines A15, A14, A13 are used for chip selection.

#### Address map

| Chip | A15 A14 A13 | Address range |
|---|---|---|
| ROM 1 | 0 1 0 | 4000H – 5FFFH |
| ROM 2 | 0 1 1 | 6000H – 7FFFH |

Check: 4000H + 2000H (8K) = 6000H, and 6000H + 2000H = 8000H, so the two chips are consecutive.

#### Decoder connections (74LS138)

- C, B, A = A15, A14, A13. Pattern 010 gives Y2' (ROM 1); 011 gives Y3' (ROM 2).
- G1 = +5 V, G2B' = GND.
- G2A' = IO/M', so the decoder works only in memory cycles (IO/M' = 0).
- Y2' → CE' of ROM 1; Y3' → CE' of ROM 2.
- A12–A0 go to the address pins of both ROMs; D7–D0 to both data outputs.
- RD' goes to OE' of both ROMs (ROM has no write).

```text
 A15 --- C \
 A14 --- B  | 74LS138      +-------+
 A13 --- A /  Y2' -------- |CE' R1 | 4000-5FFF
 IO/M' - G2A' Y3' ----+    |8Kx8   |
 GND --- G2B'         |    +-------+
 +5V --- G1           |    +-------+
                      +--- |CE' R2 | 6000-7FFF
                           |8Kx8   |
 A12-A0 --> A12-A0 of both +-------+
 RD' --> OE' of both,  D7-D0 <-- data out
```

The lower address byte is multiplexed with data on AD7–AD0, so a 74LS373 latch enabled by ALE is first used to separate A7–A0. A15–A8 are available directly. Signals marked with a prime (RD', WR', IO/M', CE', OE') are active low.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. How many address lines does an 8K x 8 ROM need and which remain for chip select?
   A. 12 lines; A15-A12
   B. 14 lines; A15, A14
   C. 13 lines (A12-A0); A15, A14, A13
   D. 8 lines; A15-A8
   Answer: C. 8K = 2^13 locations so 13 lines go to the chip, leaving A15-A13 for selection. (Key point: Address lines for 8K)

2. For ROM 2 at 6000H-7FFFH, what is A15 A14 A13?
   A. 0 1 1
   B. 0 1 0
   C. 1 1 0
   D. 0 0 1
   Answer: A. 6000H = 0110 0000..., so A15A14A13 = 011, giving Y3'. (Key point: ROM 2 pattern)

3. Which decoder outputs drive the two ROMs?
   A. Y0' and Y1'
   B. Y4' and Y5'
   C. Y6' and Y7'
   D. Y2' for ROM 1 and Y3' for ROM 2
   Answer: D. C,B,A = A15,A14,A13; 010 gives Y2' (4000H) and 011 gives Y3' (6000H). (Key point: Decoder outputs)

4. Why is only RD' connected (to OE') and not WR'?
   A. WR' is used for CE'
   B. A ROM cannot be written, so it has no write input
   C. The ROM is read through ALE
   D. WR' is connected to the decoder
   Answer: B. ROM is read only, so only RD' is needed for output enable. (Key point: Control signals for ROM)

## Related in Microprocessor

- [Interface two 4K x 8 ROM with 3:8 decoder](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-two-4k-rom-38-decoder) — Microprocessor, chapter 4
- [Address decoding for two 8 KB RAM at C000H](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-two-8kb-ram-c000h) — Microprocessor, chapter 4
- [Address decoding for 8 LEDs output port](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-output-port-8-leds) — Microprocessor, chapter 4
- [Address decoding for input and output ports](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-input-output-port-block-decoder) — Microprocessor, chapter 4
- [Address decoding for input port at 8050H](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-input-port-lda-8050h) — Microprocessor, chapter 4
- [Address decoding with PROM decoder](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aaddress-decoding-prom) — Microprocessor, chapter 4

## Related in other subjects

- [DMA concept; ROM/RAM interface at 4000H](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Adma-memory-interface-4000h) — Instrumentation II, chapter 1
- [USB interface chips: device vs host](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Ausb-interface-chips) — Instrumentation II, chapter 3
- [USB enumeration; device vs host interface chips](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Ausb-enumeration) — Instrumentation II, chapter 3
- [8086 RAM/EPROM interfacing with reset address](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Arom-ram-8086-fffffh) — Instrumentation II, chapter 1