---
title: "Address decoding for two 8 KB RAM at C000H"
subject: "Microprocessor"
chapter: 4
key: "semester_4/microprocessor:decoder-two-8kb-ram-c000h"
source: https://www.bctengineer.com/q/semester_4/microprocessor/decoder-two-8kb-ram-c000h
site: BCT Engineering
---

# Address decoding for two 8 KB RAM at C000H

Microprocessor · Chapter 4: Microprocessor System

- Asked in: 2071 Bhadra, 8 marks
- Video: [Interface 4Kbyte RAM and 2Kbyte ROM with starting address 8000H](https://www.youtube.com/watch?v=yS65OgzNKf8) — Jay Explains
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_4/microprocessor/decoder-two-8kb-ram-c000h
- Whole chapter: https://www.bctengineer.com/md/semester_4/microprocessor/chapter-4

## Question

Draw the address decoding circuit to interface two RAM memory block each of 8 KB at address C000H.

## Short answer

Each 8KB RAM uses A12–A0. Decoder 74LS138 with C,B,A = A15,A14,A13, G1=+5V, G2B'=GND, G2A'=IO/M'. Y6' selects RAM1 (C000H–DFFFH), Y7' selects RAM2 (E000H–FFFFH). RD' to OE', WR' to WE', A12–A0 to address pins, and D7–D0 connects to data bus.

## Answer

Each 8 KB RAM has 13 address lines (A12–A0). A15, A14, A13 select the chip. The two RAMs occupy consecutive blocks from C000H.

#### Address map

| Chip | A15 A14 A13 | A12–A0 | Range |
|---|---|---|---|
| RAM 1 | 1 1 0 | 0…0 to 1…1 | C000H – DFFFH |
| RAM 2 | 1 1 1 | 0…0 to 1…1 | E000H – FFFFH |

#### Circuit (74LS138)

- C, B, A = A15, A14, A13. Pattern 110 → Y6' (RAM 1); 111 → Y7' (RAM 2).
- G1 = +5 V, G2B' = GND, G2A' = IO/M' (decoder active only for memory cycles).
- Y6' → CS' of RAM 1; Y7' → CS' of RAM 2.
- A12–A0 → address pins of both RAMs.
- RD' → OE' and WR' → WE' of both RAMs; D7–D0 are bidirectional and connect to the data bus.

```text
 A15 --- C \
 A14 --- B  | 74LS138      +--------+
 A13 --- A /  Y6' -------- |CS' RAM1| C000-DFFF
 IO/M' - G2A' Y7' ----+    +--------+
 GND --- G2B'         |    +--------+
 +5V --- G1           +----|CS' RAM2| E000-FFFF
                           +--------+
 A12-A0 -> both RAMs   RD'->OE'  WR'->WE'  D7-D0 <-> both
```

The lower address byte is multiplexed with data on AD7–AD0, so a 74LS373 latch enabled by ALE is first used to separate A7–A0. A15–A8 are available directly. Signals marked with a prime (RD', WR', IO/M', CE', OE') are active low. Because A15–A13 are fully decoded, RAM 1 responds only to C000H–DFFFH and RAM 2 only to E000H–FFFFH, so there is no address overlap.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. What is the range of RAM 2 when two 8 KB RAMs start at C000H?
   A. C000H-DFFFH
   B. A000H-BFFFH
   C. E000H-EFFFH
   D. E000H-FFFFH
   Answer: D. C000H + 2000H = E000H, so RAM 2 occupies E000H-FFFFH (A15A14A13 = 111). (Key point: Address map)

2. Which outputs and select pattern does RAM 1 use?
   A. A15A14A13 = 110, Y6'
   B. A15A14A13 = 111, Y7'
   C. A15A14A13 = 100, Y4'
   D. A15A14A13 = 101, Y5'
   Answer: A. C000H = 1100 0000..., so A15A14A13 = 110, which selects Y6'. (Key point: Decoder outputs)

3. Why is G2A' connected to IO/M'?
   A. To select the RAM for I/O
   B. The decoder is active only in memory cycles (IO/M' = 0)
   C. To invert RD'
   D. To enable ALE
   Answer: B. With G2A' = IO/M', the decoder is disabled for I/O cycles so RAM is not selected by I/O addresses. (Key point: G2A' use)

4. How do RAM connections differ from ROM connections?
   A. Only RD' is used
   B. Data lines are not needed
   C. RD' goes to OE' and WR' goes to WE', with bidirectional data lines
   D. A12-A0 are not used
   Answer: C. RAM is both read and written, so it needs both OE' (from RD') and WE' (from WR'), and data pins are bidirectional. (Key point: RAM controls)

## Related in Microprocessor

- [Interface 4 KB EPROM and two 2 KB RAM](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Ainterface-4kb-eprom-two-2kb-ram) — Microprocessor, chapter 4
- [Address decoding for input and output ports](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-input-output-port-block-decoder) — Microprocessor, chapter 4
- [Address decoding for 8 LEDs output port](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-output-port-8-leds) — Microprocessor, chapter 4
- [Unique/non-unique decoding, memory mapped I/O](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aunique-nonunique-decoding-memory-mapped-io) — Microprocessor, chapter 4
- [Address decoding with PROM decoder](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aaddress-decoding-prom) — Microprocessor, chapter 4
- [Interface two 8K x 8 ROM at 4000H](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-two-8k-rom-4000h) — Microprocessor, chapter 4

## Related in other subjects

- [Full vs partial address decoding for memory](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Afull-vs-partial-decoding) — Instrumentation II, chapter 2
- [DMA concept; ROM/RAM interface at 4000H](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Adma-memory-interface-4000h) — Instrumentation II, chapter 1
- [8086 RAM/EPROM interfacing with reset address](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Arom-ram-8086-fffffh) — Instrumentation II, chapter 1
- [Address sequencing for control memory](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Aaddress-sequencer) — Computer Organization and Architecture, chapter 3, asked 7×