--- title: "EI, DI, SIM, RIM and ISR address" subject: "Microprocessor" chapter: 5 key: "semester_4/microprocessor:ei-di-sim-rim-vector-address" source: https://www.bctengineer.com/q/semester_4/microprocessor/ei-di-sim-rim-vector-address site: BCT Engineering --- # EI, DI, SIM, RIM and ISR address Microprocessor · Chapter 5: Interrupt Operations - Asked in: 2073 Magh, 8 marks - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_4/microprocessor/ei-di-sim-rim-vector-address - Whole chapter: https://www.bctengineer.com/md/semester_4/microprocessor/chapter-5 ## Question Explain the purpose of the EI, DI, SIM and RIM instructions of the 8085 processor while using interrupts. Describe how the 8085 obtains the starting address of the interrupt service routine for each of the hardware interrupts. ## Short answer EI enables maskable interrupts after next instruction; DI disables them. SIM sets masks, resets RST7.5 flip-flop, outputs serial data. RIM reads mask/pending/IE and SID. Fixed vectors: TRAP=0024H, RST7.5=003CH, RST6.5=0034H, RST5.5=002CH. INTR obtains address from external device via INTA'. ## Answer #### Purpose of the instructions | Instruction | Opcode | Purpose | |---|---|---| | **EI** | FBH | Enable interrupts: sets the interrupt enable flip-flop, so INTR, RST 5.5, 6.5, 7.5 can be accepted. The effect starts after the next instruction, so a RET can complete first. | | **DI** | F3H | Disable interrupts: resets the flip-flop; INTR and RST 5.5/6.5/7.5 are ignored. TRAP is not affected. | | **SIM** | 30H | Set Interrupt Mask: uses the accumulator to set or clear the masks of RST 5.5/6.5/7.5, to reset the RST 7.5 flip-flop, and to output serial data on SOD. | | **RIM** | 20H | Read Interrupt Mask: puts the mask bits, pending interrupt bits, the IE flag and the serial input SID into the accumulator. | #### SIM accumulator format | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |---|---|---|---|---|---|---|---| | SOD | SDE | X | R7.5 | MSE | M7.5 | M6.5 | M5.5 | - MSE = 1 allows the mask bits M7.5–M5.5 to be changed; M = 1 masks that interrupt. - R7.5 = 1 resets the RST 7.5 flip-flop. SDE = 1 enables serial output of bit SOD. Example: to enable RST 6.5 only, `MVI A,0DH ; SIM ; EI` (MSE = 1, M7.5 = 1, M6.5 = 0, M5.5 = 1). RIM format: SID, I7.5, I6.5, I5.5, IE, M7.5, M6.5, M5.5 (D7 to D0). #### How the starting address of the ISR is obtained When an interrupt is accepted, the 8085 pushes the PC on the stack and loads the PC with a fixed address, as follows. | Interrupt | Vector (starting address) | |---|---| | TRAP | 0024H | | RST 7.5 | 003CH | | RST 6.5 | 0034H | | RST 5.5 | 002CH | | INTR | Not fixed | - These addresses are 8 × n for the restart number n: TRAP acts as RST 4.5, so 4.5 × 8 = 36 = 24H; 5.5 × 8 = 44 = 2CH; 6.5 × 8 = 52 = 34H; 7.5 × 8 = 60 = 3CH. - For these four inputs the vector is internal, so no INTA' is needed. Normally a JMP to the real ISR is stored at the vector address, because only a few bytes are available between vectors. - For **INTR**, the 8085 sends INTA' and the external device puts an instruction on the data bus. It is usually RST n (vector 8 × n, from 0000H to 0038H) or a CALL instruction with a 16-bit address, so the device decides the ISR address. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What do EI and DI do in the 8085? A. EI sets and DI resets the interrupt enable flip-flop; TRAP is unaffected B. EI and DI enable and disable all interrupts including TRAP C. EI and DI set and clear the masks M5.5-M7.5 D. EI and DI send INTA' to the device Answer: A. They control the IE flip-flop for INTR and RST 5.5/6.5/7.5, but TRAP is not affected. (Key point: EI and DI effect) 2. Which accumulator value for SIM enables only RST 6.5? A. 07H B. 0DH (MSE = 1, M7.5 = 1, M6.5 = 0, M5.5 = 1) C. 0AH D. 08H Answer: B. MSE must be 1 and only M6.5 must be 0: 0000 1101 = 0DH. (Key point: SIM mask value) 3. How are the fixed vector addresses of TRAP and RST n.5 found? A. 4 x n, e.g. RST 6.5 = 26H B. 16 x n, e.g. RST 6.5 = 68H C. 8 x n, e.g. RST 6.5 = 6.5 x 8 = 34H D. n + 2CH Answer: C. These vectors are 8 x the restart number: 4.5 x 8 = 24H, 5.5 x 8 = 2CH, 6.5 x 8 = 34H, 7.5 x 8 = 3CH. (Key point: Fixed vector formula) 4. How does the 8085 get the ISR address for INTR? A. The external device supplies RST n or a CALL instruction after INTA' B. It uses a fixed address 0024H C. It reads a vector table at 4 x n D. It takes it from the SIM instruction Answer: A. INTR is non-vectored; the device puts an instruction on the data bus, so it decides the ISR address. (Key point: INTR address source) ## Related in Microprocessor - [ISR, IVT and type 0 to 4 interrupts](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aivt-ir-isr-type-0-to-4) — Microprocessor, chapter 5 - [Interrupt vs polling; interrupts in 8085](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Ainterrupt-vs-polling-8085) — Microprocessor, chapter 5 - [RIM instruction in 8085](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3A8085-rim) — Microprocessor, chapter 5 - [Classification of 8085 instructions](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3A8085-instruction-classification) — Microprocessor, chapter 2 - [Hardware interrupts available in 8086](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3A8086-hardware-interrupts) — Microprocessor, chapter 5 - [Hardware vs software interrupts](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Ahardware-vs-software-interrupts) — Microprocessor, chapter 5 ## Related in other subjects - [Interrupt and fixed ISR flow of actions](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Ainterrupt-fixed-isr-flow) — Embedded System, chapter 5 - [Fibonacci single-purpose processor](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Aspp-fibonacci) — Embedded System, chapter 2, asked 2× - [Single-purpose processor for power](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Aspp-power) — Embedded System, chapter 2, asked 2× - [Dual-purpose processor: median and variance](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Adual-purpose-median-variance) — Embedded System, chapter 2