--- title: "Fetch and execution cycle with RTL" subject: "Microprocessor" chapter: 1 key: "semester_4/microprocessor:fetch-execute-cycle-rtl" source: https://www.bctengineer.com/q/semester_4/microprocessor/fetch-execute-cycle-rtl site: BCT Engineering --- # Fetch and execution cycle with RTL Microprocessor · Chapter 1: Introduction to Microprocessor - Asked in: 2074 Bhadra, 5+3 marks - Video: [CO29 - Single Bus Organization Processor | Instruction Fetch](https://www.youtube.com/watch?v=DNEVbofZIwg) — EZCSE - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_4/microprocessor/fetch-execute-cycle-rtl - Whole chapter: https://www.bctengineer.com/md/semester_4/microprocessor/chapter-1 ## Question Explain fetch and execution cycle of an instruction of a stored program computer. Illustrate with the help of RTL specification. ## Short answer Every instruction starts with a fetch cycle: MAR←PC, MDR←M[MAR], PC←PC+1, IR←MDR, then decode. Execution varies: ADD B does A←A+B; LDA addr reads address bytes into WZ, then A←M[WZ]; JMP addr loads the target address into PC. ## Answer In a stored program computer, every instruction goes through a **fetch cycle** (bring the instruction from memory to the CPU) and an **execute cycle** (do what the instruction says). Registers used: PC (address of next instruction), MAR (memory address register), MDR/MBR (data read or to be written), IR (instruction register), AC/A (accumulator), and W, Z (temporary registers that hold a 16-bit address, WZ, for LDA and JMP). The steps below are general register transfers (t1, t2, … are micro-steps, not 8085 T-states; on the 8085, LDA takes 4 machine cycles and 13 T-states). #### Fetch cycle The control unit does the following in the first clock periods: ```text t1: MAR <- PC ; address of instruction to address bus t2: MDR <- M[MAR] ; memory read, instruction comes to MDR PC <- PC + 1 ; point to next instruction t3: IR <- MDR ; instruction goes to IR t4: decode IR ; control unit decodes opcode ``` #### Execute cycle The steps depend on the instruction. Examples: **1. ADD B (register operand, A <- A + B)** ```text t5: TEMP <- B ; B goes to the ALU's temporary register t6: A <- A + TEMP ; update flags ``` **2. LDA addr (direct memory operand, A <- M[addr])** ```text t5: MAR <- PC ; fetch low address byte t6: MDR <- M[MAR] ; PC <- PC + 1 ; Z <- MDR t7: MAR <- PC ; fetch high address byte t8: MDR <- M[MAR] ; PC <- PC + 1 ; W <- MDR t9: MAR <- WZ t10: MDR <- M[MAR] t11: A <- MDR ``` **3. JMP addr** ```text t5-t8: read address bytes into W and Z t9: PC <- WZ ``` ```text +-------+ +--------+ +---------+ | Fetch |---->| Decode |---->| Execute |--+ +-------+ +--------+ +---------+ | ^ | +--------------------------------------+ ``` After execution, the CPU returns to the fetch cycle for the next instruction. RTL makes every step a precise register transfer, which the control unit turns into control signals. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. Which sequence correctly describes the fetch cycle? A. MAR<-PC; MDR<-M[MAR], PC<-PC+1; IR<-MDR; decode B. IR<-PC; MDR<-IR; MAR<-MDR C. A<-MDR; PC<-A; MAR<-IR D. MDR<-PC; MAR<-M[MDR]; IR<-A Answer: A. PC goes to MAR, memory is read into MDR while PC is incremented, then MDR goes to IR for decoding. (Key point: Fetch RTL) 2. Why is PC <- PC+1 done during the fetch? A. To point to the next byte/instruction B. To store the result C. To clear the flags D. To select the ALU operation Answer: A. After the opcode is read, PC must point to the next byte or instruction. (Key point: PC increment timing) 3. In LDA addr, how is the 16-bit address held before the data is read? A. In W and Z (WZ), then MAR<-WZ B. In the stack pointer C. In the flag register D. In IR only Answer: A. The low and high bytes are read into Z and W; then MAR<-WZ and A<-M[MAR]. (Key point: LDA execution) 4. What is the final step for JMP addr? A. A <- WZ B. PC <- WZ C. MAR <- IR D. SP <- WZ Answer: B. After reading the address bytes into W and Z, PC<-WZ makes execution continue at the new address. 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