--- title: "Single and double handshaking" subject: "Microprocessor" chapter: 4 key: "semester_4/microprocessor:handshaking-single-double" source: https://www.bctengineer.com/q/semester_4/microprocessor/handshaking-single-double site: BCT Engineering --- # Single and double handshaking Microprocessor · Chapter 4: Microprocessor System - Asked in: 2074 Bhadra, 3 marks - Video: [ASYNCHRONOUS DATA TRANSFER(HANDSHAKING) || SINGLE HANDSHAKING || DOUBLE HANDSHAKING ||](https://www.youtube.com/watch?v=ll4cNHvpvjY) — Education-The Right Away-By Preeti Chhabra - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_4/microprocessor/handshaking-single-double - Whole chapter: https://www.bctengineer.com/md/semester_4/microprocessor/chapter-4 ## Question Explain single handshaking and double handshaking technique used in parallel interfacing with a microprocessor. ## Short answer Single handshaking uses one control line, usually a strobe or DAV, to indicate data valid; the receiver reads but no acknowledge is sent. Double handshaking uses DAV and ACK: sender asserts DAV, receiver accepts and asserts ACK, then both deassert in sequence, ensuring reliable transfer between different speeds. ## Answer **Handshaking** is the exchange of control signals between a sender and a receiver to make sure that data is transferred only when the receiver is ready and has accepted it. It is used where the two devices have different speeds. #### Single handshaking One control line is used. The sender puts data on the data lines and activates a **strobe/DAV (data valid)** signal. The receiver reads the data when it sees the strobe. The sender does not know whether the data was really accepted, so this is used when the receiver is fast. #### Double (full) handshaking Two control lines are used, **DAV/STB** from the sender and **ACK** from the receiver: 1. Sender places data and activates DAV. 2. Receiver sees DAV, reads data and activates ACK. 3. Sender sees ACK, removes DAV (and may change data). 4. Receiver sees DAV removed and removes ACK. 5. The cycle is ready for the next byte. ```text DATA ========= DAV ___|‾‾‾‾‾‾‾|______ ACK _______|‾‾‾‾‾‾|___ ``` Double handshaking is reliable for any speed. The 8255 uses it in mode 1 (STB/IBF, OBF/ACK) and mode 2. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What is the weakness of single handshaking? A. It needs two control lines B. The sender cannot know whether the data was really accepted C. It is slower than double handshake D. The receiver must send data back Answer: B. Only a data-valid strobe is sent, with no acknowledgement, so it is used only when the receiver is fast. (Key point: Limit of single handshake) 2. In double handshaking, what does the sender do when it sees ACK? A. Activates DAV again B. Changes ACK C. Removes DAV (and may change the data) D. Waits for the receiver to remove DAV Answer: C. After ACK the sender removes DAV; the receiver then removes ACK, and the next byte can be sent. (Key point: Double handshake step) 3. Why is double handshaking preferred for devices of different speeds? A. Each step waits for the other side, so it is reliable at any speed B. It is faster than single handshake C. It uses only one wire D. It needs no control signals Answer: A. Because the sender and receiver acknowledge each stage, transfer is safe whatever the speed difference; the 8255 uses it in modes 1 and 2. (Key point: Why double handshake) ## Related in Microprocessor - [RS-232 signals, handshaking, DTE-DCE](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Ars232-signals-dte-dce) — Microprocessor, chapter 4, asked 3× - [74LS138 interfacing of ROM, RAM, EPROM](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-74ls138-rom-ram-eprom) — Microprocessor, chapter 4 - [Interfacing 2732 EPROM and 6116 RAM](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-74ls138-2732-6116) — Microprocessor, chapter 4 - [Memory capacity from range and interfacing](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Amemory-range-capacity-interfacing) — Microprocessor, chapter 4 - [Six stage pipeline technique](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Asix-stage-pipeline) — Microprocessor, chapter 6 - [Short note: serial and parallel interface](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aserial-parallel-interface) — Microprocessor, chapter 4 ## Related in other subjects - [Single, double, multiple timber roofs; king post truss](https://www.bctengineer.com/question.md?key=semester_6%2Fbuilding_technology%3Atimber-roofs-king-post) — Building Technology, chapter 4, asked 2× - [Single vs double earth wire selection](https://www.bctengineer.com/question.md?key=semester_8%2Ftransmission_and_distribution_system_design%3Asingle-double-earth-wire-criteria) — Transmission and Distribution System Design, chapter 3 - [T/F: double earth wire for 400 kV single circuit](https://www.bctengineer.com/question.md?key=semester_8%2Ftransmission_and_distribution_system_design%3Atf-400kv-single-circuit-double-earth) — Transmission and Distribution System Design, chapter 3 - [T/F: tower height same for single/double circuit](https://www.bctengineer.com/question.md?key=semester_8%2Ftransmission_and_distribution_system_design%3Atf-tower-height-single-double-circuit) — Transmission and Distribution System Design, chapter 4