---
title: "Instruction cycle and machine cycle"
subject: "Microprocessor"
chapter: 1
key: "semester_4/microprocessor:instruction-cycle-machine-cycle"
source: https://www.bctengineer.com/q/semester_4/microprocessor/instruction-cycle-machine-cycle
site: BCT Engineering
---

# Instruction cycle and machine cycle

Microprocessor · Chapter 1: Introduction to Microprocessor

- Asked in: 2071 Magh, 4 marks; 2069 Bhadra, 4 marks (asked 2 times)
- Video: [Unit1  L15| Instruction cycle | Machine Cycle | T state](https://www.youtube.com/watch?v=nvuMoojr8_E) — Techno Tutorials ( e-Learning)
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_4/microprocessor/instruction-cycle-machine-cycle
- Whole chapter: https://www.bctengineer.com/md/semester_4/microprocessor/chapter-1

## Question

Define instruction cycle and machine cycle.

## Short answer

The instruction cycle is the total time to fetch and execute one instruction, composed of one or more machine cycles. A machine cycle is the time for a basic memory or I/O access (e.g., opcode fetch, read, write), lasting 3 to 6 T-states (clock periods).

## Answer

#### Instruction cycle
The **instruction cycle** is the total time taken by the microprocessor to fetch an instruction from memory and execute it. It is made of one or more machine cycles. For example, `MOV A,B` has 1 machine cycle; `LDA 2050H` has 4 machine cycles.

#### Machine cycle
A **machine cycle** is the time required to complete one basic operation of accessing memory or an I/O device, such as opcode fetch, memory read, memory write, I/O read or I/O write. Each machine cycle consists of 3 to 6 clock periods called **T-states**.

#### T-state
One T-state is one period of the system clock (T = 1 / clock frequency). It is the smallest unit of timing.

#### 8085 machine cycles
| Machine cycle | T-states | IO/M | S1 | S0 |
|---|---|---|---|---|
| Opcode fetch | 4 (sometimes 6) | 0 | 1 | 1 |
| Memory read | 3 | 0 | 1 | 0 |
| Memory write | 3 | 0 | 0 | 1 |
| I/O read | 3 | 1 | 1 | 0 |
| I/O write | 3 | 1 | 0 | 1 |
| Interrupt acknowledge | 6 (first, opcode) / 3 (others) | 1 | 1 | 1 |

#### Relation
```text
1 instruction cycle = 1 to 5 machine cycles
1 machine cycle     = 3 to 6 T-states
```
The first machine cycle of every instruction is always the opcode fetch. There is also a **bus idle** cycle, when the buses are not used (e.g. during the internal 16-bit addition of DAD).

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. What is an instruction cycle?
   A. Time of one clock period
   B. Time to fetch and execute a whole instruction
   C. Time for one memory read only
   D. Time between two interrupts
   Answer: B. It is the total time to fetch and execute an instruction and has one or more machine cycles. (Key point: Instruction cycle)

2. A machine cycle in the 8085 consists of:
   A. 1 to 2 T-states
   B. 3 to 6 T-states
   C. 7 to 10 T-states
   D. Exactly 4 T-states always
   Answer: B. Each machine cycle is 3 to 6 clock periods (T-states). (Key point: Machine cycle composition)

3. Which 8085 machine cycle has IO/M = 0, S1 = 1, S0 = 1?
   A. Memory read
   B. Memory write
   C. Opcode fetch
   D. I/O read
   Answer: C. Opcode fetch uses IO/M=0, S1=1, S0=1; it is always the first machine cycle of an instruction. (Key point: Opcode fetch status)

## Related in Microprocessor

- [Machine cycle, T-states, ANI 55H timing](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Amachine-cycle-tstate-ani-55h) — Microprocessor, chapter 2
- [Machine cycles involved in LDA](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Amachine-cycles-lda) — Microprocessor, chapter 2, asked 2×
- [Stored program concept and processing cycle](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Astored-program-processing-cycle) — Microprocessor, chapter 1, asked 6×
- [Fetch and execution cycle with RTL](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Afetch-execute-cycle-rtl) — Microprocessor, chapter 1

## Related in other subjects

- [Instruction cycle state diagram with interrupt](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Ainstr-cycle) — Computer Organization and Architecture, chapter 1, asked 6×
- [Retentivity, coercivity, energy per cycle](https://www.bctengineer.com/question.md?key=semester_4%2Felectrical_machine%3Aretentivity-coercivity-energy-loop) — Electrical Machine, chapter 1