--- title: "Interface 4 KB EPROM and two 2 KB RAM" subject: "Microprocessor" chapter: 4 key: "semester_4/microprocessor:interface-4kb-eprom-two-2kb-ram" source: https://www.bctengineer.com/q/semester_4/microprocessor/interface-4kb-eprom-two-2kb-ram site: BCT Engineering --- # Interface 4 KB EPROM and two 2 KB RAM Microprocessor · Chapter 4: Microprocessor System - Asked in: 2072 Magh, 8 marks - Video: [U1 L31 | Interfacing of 8085 Microprocessor with 4KB memory | Memory interfacing with 8085 MP](https://www.youtube.com/watch?v=csH5djL2uWM) — Techno Tutorials ( e-Learning) - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_4/microprocessor/interface-4kb-eprom-two-2kb-ram - Whole chapter: https://www.bctengineer.com/md/semester_4/microprocessor/chapter-4 ## Question Design an interfacing circuit to interface one 4 KB EPROM and two 2 KB R/W memory for 8085 microprocessor. ## Short answer EPROM 4K at 0000H–0FFFH, RAM1 2K at 1000H–17FFH, RAM2 2K at 1800H–1FFFH. Decoder: 74LS138 with C,B,A = A13,A12,A11; G1=+5V, G2A'=IO/M', G2B'=A15 OR A14. Y0' and Y1' ANDed drive CE' of EPROM; Y2' and Y3' drive CS' of RAM1 and RAM2. A11–A0 to EPROM, A10–A0 to RAMs, RD' to OE', WR' to WE'. ## Answer Sizes: 4 KB EPROM = 4096 bytes → 12 address lines (A11–A0). 2 KB RAM = 2048 bytes → 11 address lines (A10–A0). #### Memory map | Device | Range | A15 A14 A13 A12 A11 | |---|---|---| | EPROM 4K | 0000H – 0FFFH | 0 0 0 0 x | | RAM 1 2K | 1000H – 17FFH | 0 0 0 1 0 | | RAM 2 2K | 1800H – 1FFFH | 0 0 0 1 1 | The EPROM is placed at 0000H because the 8085 starts at 0000H after reset and needs the start-up program in non-volatile memory. #### Decoder circuit (74LS138) - C, B, A = A13, A12, A11. - EPROM: 000 and 001 → Y0', Y1' joined by an AND gate → CE'. - RAM 1: 010 → Y2' → CS'. RAM 2: 011 → Y3' → CS'. - G1 = +5 V, G2A' = IO/M', G2B' = A15 OR A14 (both must be 0). - RD' → OE' of EPROM and both RAMs; WR' → WE' of both RAMs. ```text A13 -- C \ A12 -- B | 74LS138 A11 -- A / Y0' -+--[AND]--CE' EPROM 4K IO/M' - G2A' Y1' -+ (0000-0FFF) A15,A14 -[OR]- G2B' +5V ----- G1 Y2' ---------- CS' RAM1 (1000-17FF) Y3' ---------- CS' RAM2 (1800-1FFF) A11-A0 -> EPROM, A10-A0 -> RAMs RD' -> OE' all, WR' -> WE' RAMs, D7-D0 common ``` The lower address byte is multiplexed with data on AD7–AD0, so a 74LS373 latch enabled by ALE is first used to separate A7–A0. A15–A8 are available directly. Signals marked with a prime (RD', WR', IO/M', CE', OE') are active low. Only one chip is selected at a time, so the data bus has no conflict. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What is the address range of RAM 2 (2 KB) in this design? A. 1000H-17FFH B. 1800H-1FFFH C. 0800H-0FFFH D. 2000H-27FFH Answer: B. RAM 1 is 1000H-17FFH, and the next 2 KB (pattern 00011) is 1800H-1FFFH. (Key point: RAM 2 range) 2. How is the 4 KB EPROM chip enable produced? A. From Y2' alone B. From Y7' C. From Y3' alone D. From an AND of Y0' and Y1' Answer: D. 4 KB spans two 2 KB decoder blocks (000 and 001), so Y0' and Y1' are ANDed. (Key point: EPROM select) 3. What is G2B' connected to and why? A. IO/M' only B. A15 OR A14, so the decoder is enabled only when both are 0 C. A15 AND A14 D. +5 V Answer: B. All devices are below 2000H so A15 = A14 = 0 is required; the OR output is 0 only then. (Key point: G2B' logic) 4. Why is there no data-bus conflict? A. Because RD' is always high B. Because EPROM is read only C. Because ALE disables the chips D. Only one chip select is low at a time, so only one device drives the data bus Answer: D. The decoder produces only one active-low select for any address, so only one chip drives the bus. (Key point: No bus conflict) ## Related in Microprocessor - [74LS138 interfacing of ROM, RAM, EPROM](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-74ls138-rom-ram-eprom) — Microprocessor, chapter 4 - [Address decoding for two 8 KB RAM at C000H](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-two-8kb-ram-c000h) — Microprocessor, chapter 4 - [Interfacing 2732 EPROM and 6116 RAM](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-74ls138-2732-6116) — Microprocessor, chapter 4 - [Memory capacity from range and interfacing](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Amemory-range-capacity-interfacing) — Microprocessor, chapter 4 - [Interface two 8K x 8 ROM at 4000H](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-two-8k-rom-4000h) — Microprocessor, chapter 4 - [Interface two 4K x 8 ROM with 3:8 decoder](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-two-4k-rom-38-decoder) — Microprocessor, chapter 4 ## Related in other subjects - [8086 RAM/EPROM interfacing with reset address](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Arom-ram-8086-fffffh) — Instrumentation II, chapter 1 - [Interfacing: 512-byte RAM with 8085](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Arag-ram-512-interface) — Instrumentation II, chapter 2 - [Memory-mapped I/O design for 8085](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Amemmapped-io-design-1000h) — Instrumentation II, chapter 2 - [DMA concept; ROM/RAM interface at 4000H](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Adma-memory-interface-4000h) — Instrumentation II, chapter 1