--- title: "Interrupts and handling with single INTR pin" subject: "Microprocessor" chapter: 5 key: "semester_4/microprocessor:interrupt-importance-single-intr" source: https://www.bctengineer.com/q/semester_4/microprocessor/interrupt-importance-single-intr site: BCT Engineering --- # Interrupts and handling with single INTR pin Microprocessor · Chapter 5: Interrupt Operations - Asked in: 2072 Asoj, 1+2+5 marks - Video: [Interrupts in 8085 microprocessor | Types of Interrupts in Computer Organization](https://www.youtube.com/watch?v=1aG3aFEKxyA) — Gate Smashers - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_4/microprocessor/interrupt-importance-single-intr - Whole chapter: https://www.bctengineer.com/md/semester_4/microprocessor/chapter-5 ## Question What is interrupt? What is its importance in microprocessor? How interrupts from different peripherals can be handled with single INTR pin in 8086 microprocessor? Explain. ## Short answer An interrupt pauses the main program to execute an ISR, improving CPU utilization and response time. Multiple peripherals on one INTR pin use an 8259A PIC which prioritizes requests and supplies the type number during INTA cycles. ## Answer #### Interrupt An interrupt is a signal (hardware) or an instruction (software) that makes the processor stop its present program temporarily, execute a special routine called the interrupt service routine (ISR) for the event, and then return to the program where it stopped. #### Importance - The CPU does not waste time polling devices continuously; it does useful work until a device needs service, so CPU utilisation is higher. - Fast response to real-time events (power failure, keyboard press, timer). - Allows slow devices and the fast CPU to work together efficiently. - Allows software services (system calls) and error handling (divide error, overflow). - Gives priority to important tasks and supports multitasking systems. #### Handling many devices with the single INTR pin of the 8086 The 8086 has only one maskable interrupt input, INTR. To connect several devices, a **programmable interrupt controller 8259A** is placed between devices and the CPU. ```text Dev0 --IR0 +---------+ Dev1 --IR1 | |--INT--> INTR (8086) ... | 8259A |<--INTA'-- INTA' (8086) Dev7 --IR7 | |<->D7-D0<-> data bus +---------+ ``` 1. Up to 8 devices connect to IR0–IR7. When one or more raise their requests, the 8259A latches them in its IRR, checks the mask (IMR), and resolves priority. 2. It sends the signal INT to INTR of the 8086. 3. If IF = 1, the 8086 sends two INTA' pulses. 4. On the second INTA' the 8259A places the type number of the highest-priority request on D7–D0 (the base type set during initialisation plus the IR number). 5. The 8086 uses the type number to read the ISR address from the interrupt vector table, and serves that device. 6. The ISR gives an end-of-interrupt command (EOI) to the 8259A at the end. More than 8 devices: up to 8 slave 8259A can be cascaded to one master, giving 64 interrupt levels on the single INTR pin. Other methods are polling and daisy-chaining, but the PIC is the standard method. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. Why are interrupts better than polling? A. The CPU does useful work until a device needs service, so utilisation is higher B. Interrupts need no extra hardware C. The CPU checks every device in a loop D. They make the CPU slower but simpler Answer: A. Polling wastes time in status loops; with interrupts, devices call the CPU only when needed. (Key point: Importance) 2. How can many devices share the single INTR pin of the 8086? A. By connecting all devices directly to INTR B. By using an 8259A programmable interrupt controller between the devices and INTR C. By using the NMI pin for each device D. By using more TRAP pins Answer: B. The 8259A collects requests from IR0-IR7, resolves priority and sends one INT to INTR. (Key point: Single INTR solution) 3. How does the 8086 learn which device interrupted when using the 8259A? A. The CPU polls each IR line B. The device writes its address in the IVT C. The 8259A puts the type number on D7-D0 during the second INTA' pulse D. The type number is always 2 Answer: C. After two INTA' pulses, the 8259A places the type number, which the CPU uses to read the vector table. (Key point: Type number delivery) 4. How many interrupt levels can be reached by cascading 8259As on one INTR pin? A. 64 (one master and 8 slaves) B. 16 C. 8 only, cascading is impossible D. 256 Answer: A. Up to 8 slaves on one master give 8 x 8 = 64 levels. (Key point: Number of levels) ## Related in Microprocessor - [Hardware interrupts available in 8086](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3A8086-hardware-interrupts) — Microprocessor, chapter 5 - [Interrupt processing in 8086](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Ainterrupt-processing-8086) — Microprocessor, chapter 5, asked 3× - [Interrupt vs polling; interrupts in 8085](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Ainterrupt-vs-polling-8085) — Microprocessor, chapter 5 - [Interrupt vector table and its use](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aivt-interrupt-handling) — Microprocessor, chapter 5, asked 3× - [ISR, IVT and type 0 to 4 interrupts](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aivt-ir-isr-type-0-to-4) — Microprocessor, chapter 5 - [IVT in 8086 and ISR execution sequence](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aivt-8086-isr-execution-sequence) — Microprocessor, chapter 5 ## Related in other subjects - [How interrupts interface with microprocessor](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Ainterrupt-interface-microprocessor) — Embedded System, chapter 5 - [Calls handled by 30 servers carrying 15 E](https://www.bctengineer.com/question.md?key=semester_8%2Ftelecommunications%3Aservers-15e-calls-per-hour) — Telecommunications, chapter 6, asked 3× - [Calls handled by 25 servers carrying 5 E](https://www.bctengineer.com/question.md?key=semester_8%2Ftelecommunications%3Aservers-25-5e-calls) — Telecommunications, chapter 6, asked 3×