---
title: "Sequence of steps when interrupt occurs"
subject: "Microprocessor"
chapter: 5
key: "semester_4/microprocessor:interrupt-occurrence-steps"
source: https://www.bctengineer.com/q/semester_4/microprocessor/interrupt-occurrence-steps
site: BCT Engineering
---

# Sequence of steps when interrupt occurs

Microprocessor · Chapter 5: Interrupt Operations

- Asked in: 2074 Bhadra, 2 marks; 2070 Magh, 6 marks (asked 2 times)
- Video: [Interrupt Service Routine in 8085 Microprocessor: Execution and Steps | 8085](https://www.youtube.com/watch?v=6vb0KzgfZ4I) — Engineering Funda
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_4/microprocessor/interrupt-occurrence-steps
- Whole chapter: https://www.bctengineer.com/md/semester_4/microprocessor/chapter-5

## Question

Write down the general sequence of steps followed when an interrupt occurs.

## Short answer

Device sends request; CPU finishes instruction, if allowed acknowledges; pushes return address and flags disabling interrupts; obtains ISR address (fixed or from IVT); executes ISR, saving registers; returns with IRET/RET restoring context.

## Answer

When a device requests an interrupt, the processor follows this sequence.

1. The device sends an interrupt request signal (for example INTR).
2. The processor finishes the instruction that is being executed. It does not stop in the middle of an instruction.
3. The processor checks whether the interrupt is allowed (the interrupt-enable flag is set and no higher-priority interrupt is in service).
4. It sends an interrupt acknowledge signal (INTA') to the device.
5. It saves the current status: the contents of the program counter (return address) and, in the 8086, the flags, are pushed onto the stack. Further interrupts are disabled.
6. It finds the address of the interrupt service routine (ISR). This is either fixed (RST, TRAP in 8085) or taken from the interrupt vector table using the type number (8086).
7. The PC (CS:IP) is loaded with that address, and the ISR executes. The ISR saves any registers it uses and services the device.
8. The ISR ends with a return instruction (RET in 8085, IRET in 8086). The saved values are popped from the stack; on the 8085 the ISR executes EI before RET to enable interrupts again, while IRET on the 8086 restores IF with the flags.
9. The processor continues the interrupted program from the next instruction.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. When does the processor respond to an interrupt request?
   A. After finishing the instruction being executed
   B. Immediately, even in the middle of an instruction
   C. Only after the whole program ends
   D. After the next 10 clock cycles regardless of the instruction
   Answer: A. The processor completes the current instruction before checking and accepting the interrupt. (Key point: When the CPU responds)

2. Which condition does the processor check before accepting a maskable interrupt?
   A. That the stack is empty
   B. That the accumulator is zero
   C. That interrupts are enabled and no higher-priority interrupt is in service
   D. That the ISR address is stored in ROM
   Answer: C. The interrupt-enable flag must be set and no higher-priority interrupt must be in service. (Key point: Check before acceptance)

3. What is saved on the stack when an 8086 interrupt is accepted?
   A. Only the accumulator
   B. The return address (CS:IP) and the flags
   C. All general-purpose registers automatically
   D. Only the ISR address
   Answer: B. The return address and flags are pushed so the interrupted program can resume later. (Key point: State saved)

4. How does the ISR return to the interrupted program in the 8086?
   A. IRET pops IP, CS and flags, restoring IF
   B. RET pops only IP and IF stays cleared
   C. JMP to the saved IP address
   D. EI followed by RET, as in the 8085
   Answer: A. IRET restores IP, CS and FLAGS, so IF is restored with the flags. The 8085 uses EI then RET. (Key point: Return from ISR)

## Related in Microprocessor

- [IVT in 8086 and ISR execution sequence](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aivt-8086-isr-execution-sequence) — Microprocessor, chapter 5

## Related in other subjects

- [Interrupt processing steps](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Ainterrupt-processing-steps) — Embedded System, chapter 5
- [IC manufacturing steps; top-down F = xz + y](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Aic-manufacturing-steps-topdown-xz-y) — Embedded System, chapter 8
- [Sequence of call steps in SS7](https://www.bctengineer.com/question.md?key=semester_8%2Ftelecommunications%3Ass7-call-steps-sequence) — Telecommunications, chapter 5
- [Interrupt driven data transfer](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Ainterrupt-driven-transfer) — Instrumentation II, chapter 1, asked 2×