--- title: "Interrupt processing in 8086" subject: "Microprocessor" chapter: 5 key: "semester_4/microprocessor:interrupt-processing-8086" source: https://www.bctengineer.com/q/semester_4/microprocessor/interrupt-processing-8086 site: BCT Engineering --- # Interrupt processing in 8086 Microprocessor · Chapter 5: Interrupt Operations - Asked in: 2075 Baisakh, 4 marks; 2071 Bhadra, 8 marks; 2069 Poush, 6 marks (asked 3 times) - Video: [Interrupt Service Routine (ISR) and Execution in 8086 Microprocessor: Detailed Steps | 8086](https://www.youtube.com/watch?v=A6GD83oDSu8) — Engineering Funda - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_4/microprocessor/interrupt-processing-8086 - Whole chapter: https://www.bctengineer.com/md/semester_4/microprocessor/chapter-5 ## Question Explain how a (hardware) interrupt is processed in 8086 microprocessor. ## Short answer For INTR, after current instruction if IF=1, 8086 runs two INTA' cycles; the second loads an 8-bit type number from PIC. It then pushes FLAGS, clears IF/TF, pushes CS:IP, loads new CS:IP from IVT at 4×type. After ISR, IRET restores. NMI uses fixed type 2, no INTA'. ## Answer A hardware interrupt in the 8086 comes from an external device on the **INTR** pin (maskable, level-triggered) or the **NMI** pin (non-maskable, rising-edge triggered, type 2). The 8086 services it after finishing the current instruction. #### INTR interrupt (maskable) – sequence 1. An external device (usually through an 8259A PIC) raises INTR. 2. At the end of the current instruction the 8086 checks INTR. It is accepted only if the interrupt flag **IF = 1**. 3. The 8086 runs **two INTA' (interrupt acknowledge) bus cycles**. The first cycle tells the PIC that the request has been accepted. In the second cycle the PIC places the 8-bit **interrupt type number** (0–255) on D7–D0, and the 8086 reads it. 4. The 8086 pushes the flag register on the stack (SP ← SP − 2). 5. It clears IF and TF, so that no other INTR or single-stepping takes place inside the routine. 6. It pushes CS, then IP (the return address of the next instruction). 7. It multiplies the type number by 4 to get the vector address. It loads the new IP from addresses 4×type and 4×type + 1, and the new CS from 4×type + 2 and 4×type + 3 of the interrupt vector table. 8. The interrupt service routine (ISR) executes. If nesting is wanted, the ISR executes STI. 9. IRET at the end pops IP, CS and the flags, and the main program resumes. #### NMI interrupt - NMI is not affected by IF and needs no INTA' cycles and no external type number. - The type is fixed as **2**, so the vector is read from addresses 00008H–0000BH. - The remaining steps (push flags, clear IF and TF, push CS and IP, load CS:IP, run the ISR, IRET) are the same. - It is used for power failure and memory parity errors. ```text Device -> INTR ----------------> 8086 8086 -> INTA' (1st): "acknowledged" 8086 -> INTA' (2nd): PIC puts type n on D7-D0 Push FLAGS, CS, IP; IF=0, TF=0 IP <- [4n], CS <- [4n+2] -> run ISR -> IRET ``` **Example:** type 40H → vector at 4×40H = 0100H; the new IP is read from 00100H–00101H and CS from 00102H–00103H. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What happens in the two INTA' cycles for an INTR interrupt? A. The CPU sends the type number to the PIC in the second cycle B. The PIC pushes the flags on the stack C. First cycle gets the type number, second cycle acknowledges D. First INTA' tells the PIC the request is accepted; in the second the PIC places the 8-bit type number on D7-D0 Answer: D. The first INTA' acknowledges the request, and in the second the PIC supplies the interrupt type number which the 8086 reads. (Key point: INTA cycles) 2. For interrupt type 40H, where does the 8086 read the new IP and CS? A. From 00040H B. IP from 00100H-00101H and CS from 00102H-00103H C. IP from 00080H D. CS from 00100H and IP from 00102H Answer: B. Vector address = 4 x type = 4 x 40H = 100H; IP is read from [4n, 4n+1] and CS from [4n+2, 4n+3]. (Key point: Vector address) 3. Which is true about the NMI in the 8086? A. It needs two INTA' cycles B. It is masked by IF = 0 C. It has a type supplied by the PIC D. It has fixed type 2 (vector at 00008H), is not affected by IF, and needs no INTA' cycles Answer: D. NMI is non-maskable, uses type 2 so the vector is at 00008H-0000BH, and needs no external type number. (Key point: NMI) ## Related in Microprocessor - [Hardware interrupts available in 8086](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3A8086-hardware-interrupts) — Microprocessor, chapter 5 - [Interrupt vector table and its use](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aivt-interrupt-handling) — Microprocessor, chapter 5, asked 3× - [IVT in 8086 and ISR execution sequence](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aivt-8086-isr-execution-sequence) — Microprocessor, chapter 5 - [Interrupt vs polling; interrupts in 8085](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Ainterrupt-vs-polling-8085) — Microprocessor, chapter 5 - [8086 speed over 8-bit; major registers](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3A8086-faster-registers) — Microprocessor, chapter 3 - [Hardware vs software interrupts](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Ahardware-vs-software-interrupts) — Microprocessor, chapter 5 ## Related in other subjects - [Interrupt processing steps](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Ainterrupt-processing-steps) — Embedded System, chapter 5 - [MIS vs DSS information and processing](https://www.bctengineer.com/question.md?key=semester_8%2Finformation_system%3Amis-vs-dss-information-processing) — Information System, chapter 4