---
title: "Interrupt vs polling; interrupts in 8085"
subject: "Microprocessor"
chapter: 5
key: "semester_4/microprocessor:interrupt-vs-polling-8085"
source: https://www.bctengineer.com/q/semester_4/microprocessor/interrupt-vs-polling-8085
site: BCT Engineering
---

# Interrupt vs polling; interrupts in 8085

Microprocessor · Chapter 5: Interrupt Operations

- Asked in: 2068 Bhadra, 2+6 marks
- Video: [Interrupt and Polling | Interrupt vs Polling | Difference between Interrupt and Polling](https://www.youtube.com/watch?v=Zcm0yLKSQvc) — Embedded System Creations
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_4/microprocessor/interrupt-vs-polling-8085
- Whole chapter: https://www.bctengineer.com/md/semester_4/microprocessor/chapter-5

## Question

How is interrupt processing different than polling? Explain how interrupt processing is done with 8085.

## Short answer

Polling wastes CPU time by repeatedly checking devices; interrupts let devices signal the CPU. In the 8085, after finishing the current instruction, it pushes PC, loads the vector address (e.g., 003CH for RST 7.5), and executes the ISR ending with EI and RET.

## Answer

#### Interrupt vs polling

In **polling** the processor repeatedly reads the status of each I/O device in a loop to see which one needs service. In **interrupt processing** the device itself signals the processor when it needs service, and the processor meanwhile does other work.

| Basis | Polling | Interrupt |
|---|---|---|
| Who starts the transfer | The CPU checks the device | The device requests the CPU |
| CPU time | Wasted in the status loop (busy waiting) | Used for useful work until an interrupt comes |
| Response time | Depends on the loop; may be slow | Fast (after current instruction) |
| Hardware | Simple, no extra hardware | Needs interrupt pins/controller |
| Priority | Fixed by order of checking | Set by hardware priority |
| Suitable for | Few devices, simple systems | Real-time, many devices |

#### Interrupt processing in the 8085

The 8085 has TRAP, RST 7.5, RST 6.5, RST 5.5 (vectored) and INTR (non-vectored), with INTA' as the acknowledge output.

1. The main program enables interrupts with **EI** (and SIM if RST 5.5/6.5/7.5 masks need to be set). TRAP is always enabled.
2. A device raises a request on one of the pins.
3. The 8085 finishes the current instruction and checks the pins (priority: TRAP > RST 7.5 > 6.5 > 5.5 > INTR).
4. If the interrupt is accepted, the interrupt enable flip-flop is reset, so no other maskable interrupt is accepted.
5. The PC (return address) is pushed on the stack.
6. For INTR, the 8085 sends INTA'; the device places an RST n opcode (or CALL) on the data bus. For the others the PC is loaded with a fixed address: TRAP 0024H, RST 7.5 003CH, RST 6.5 0034H, RST 5.5 002CH.
7. The interrupt service routine runs. It saves registers with PUSH, services the device, restores the registers with POP, and executes **EI** and then **RET**.
8. RET pops the PC and the main program continues.

```text
 Main program ---- interrupt arrives
      |   finish instruction, push PC
      v
 Vector (e.g. 003CH) -> JMP ISR
      |   ISR: PUSH, service, POP, EI, RET
      v
 Pop PC -> back to main program
```

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. What is the main difference between polling and interrupts?
   A. In polling the CPU checks devices; in interrupts the device requests the CPU
   B. In polling the device requests the CPU; in interrupts the CPU checks devices
   C. Polling needs an interrupt controller
   D. Interrupts waste CPU time in a loop
   Answer: A. Polling is busy waiting by the CPU; interrupts let the CPU work until a device signals. (Key point: Polling vs interrupt)

2. How does a typical 8085 ISR end?
   A. IRET only
   B. Restore registers with POP, then EI and RET
   C. DI and HLT
   D. RET with no EI, as interrupts re-enable automatically
   Answer: B. The 8085 disables the interrupt flip-flop on acceptance, so the ISR executes EI before RET. (Key point: Return mechanism in 8085 ISR)

3. Which are the fixed vector addresses in the 8085?
   A. TRAP 0024H, RST 7.5 003CH, RST 6.5 0034H, RST 5.5 002CH
   B. TRAP 0003H, RST 7.5 0007H, RST 6.5 0006H, RST 5.5 0005H
   C. TRAP 003CH, RST 7.5 0024H, RST 6.5 002CH, RST 5.5 0034H
   D. All at 0000H
   Answer: A. The addresses are 8 x restart number. (Key point: Fixed vectors)

4. What happens to the interrupt enable flip-flop when an 8085 interrupt is accepted?
   A. It is set to allow nesting
   B. It is unchanged
   C. It is reset, so no other maskable interrupt is accepted until EI
   D. It is read into the accumulator
   Answer: C. Further maskable interrupts are blocked until the ISR executes EI. (Key point: After acceptance)

## Related in Microprocessor

- [Software interrupts of 8085](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3A8085-software-interrupts) — Microprocessor, chapter 5
- [Interrupt pins of 8085](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3A8085-interrupt-pins) — Microprocessor, chapter 5
- [8085 ALP: transfer data with more than 3 ones](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aalp-8085-ones-greater-than-3) — Microprocessor, chapter 2
- [Interrupt processing in 8086](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Ainterrupt-processing-8086) — Microprocessor, chapter 5, asked 3×
- [Maskable vs non-maskable interrupts](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Amaskable-vs-nonmaskable) — Microprocessor, chapter 5, asked 2×
- [Hardware vs software interrupts](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Ahardware-vs-software-interrupts) — Microprocessor, chapter 5

## Related in other subjects

- [Interrupt processing steps](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Ainterrupt-processing-steps) — Embedded System, chapter 5
- [Programmed vs interrupt-driven vs DMA](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Aio-techniques-compare) — Computer Organization and Architecture, chapter 7, asked 5×
- [DMA vs programmed and interrupt-driven I/O](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Adma-overcomes) — Computer Organization and Architecture, chapter 7, asked 3×
- [Interpret: computers and word processing](https://www.bctengineer.com/question.md?key=semester_5%2Fcommunication_english%3Ainterpret-computers-solved-problems) — Communication English, chapter 1