---
title: "IVT in 8086 and ISR execution sequence"
subject: "Microprocessor"
chapter: 5
key: "semester_4/microprocessor:ivt-8086-isr-execution-sequence"
source: https://www.bctengineer.com/q/semester_4/microprocessor/ivt-8086-isr-execution-sequence
site: BCT Engineering
---

# IVT in 8086 and ISR execution sequence

Microprocessor · Chapter 5: Interrupt Operations

- Asked in: 2069 Bhadra, 3+5 marks
- Video: [Interrupt Service Routine (ISR) and Execution in 8086 Microprocessor: Detailed Steps | 8086](https://www.youtube.com/watch?v=A6GD83oDSu8) — Engineering Funda
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_4/microprocessor/ivt-8086-isr-execution-sequence
- Whole chapter: https://www.bctengineer.com/md/semester_4/microprocessor/chapter-5

## Question

Explain how the interrupt vector table is used in 8086 microprocessor. Show the complete instruction execution sequence when interrupt service routine is called.

## Short answer

For an interrupt, the 8086 pushes FLAGS, CS, and IP, clears IF and TF, then reads IP and CS from the vector address 4×type and jumps to the ISR. The ISR ends with IRET, which pops the return address and flags.

## Answer

#### Use of the interrupt vector table

The IVT occupies 00000H–003FFH and holds 256 four-byte vectors (IP then CS). For interrupt type *n*, the 8086 reads the new IP from address 4n and the new CS from 4n + 2. The type number comes from the INT n instruction, from a fixed value (types 0–4), or from the interrupt controller during the INTA' cycles of INTR. Because the table is in memory, the user can change a vector and so install his or her own ISR.

#### Complete sequence (example: INT 21H)

Assume SP = 1000H and the next instruction address is CS:IP.

1. The 8086 fetches and decodes **INT 21H** (CDH 21H). IP now points to the next instruction.
2. **Push flags:** SP ← SP − 2 = 0FFEH; flag register stored.
3. **Clear IF and TF** (IF = 0, TF = 0) to disable INTR and single stepping.
4. **Push CS:** SP ← 0FFCH.
5. **Push IP** (return address): SP ← 0FFAH.
6. Calculate the vector address: 21H × 4 = 0084H.
7. **IP ← word at 00084H**, **CS ← word at 00086H**.
8. The next instruction is fetched from the new CS:IP, i.e. the ISR starts.
9. The ISR executes (it saves registers with PUSH if it uses them).
10. **IRET** (CFH): pop IP (SP = 0FFCH), pop CS (SP = 0FFEH), pop flags (SP = 1000H). Original IF and TF are restored.
11. The main program continues with the instruction after INT 21H.

```text
 Stack after step 5 (grows down)
 SP -> 0FFAH : IP (return)
       0FFCH : CS (return)
       0FFEH : FLAGS
       1000H : (old top)
```

For hardware INTR the sequence is the same, except that step 1 is replaced by two INTA' cycles that bring the type number.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. For interrupt type n, where does the 8086 read the new IP and CS?
   A. IP from 4n and CS from 4n + 2
   B. CS from 4n and IP from 4n + 2
   C. IP from n and CS from n + 1
   D. Both from 4n
   Answer: A. Each 4-byte entry holds IP first and then CS. (Key point: Vector read)

2. In what order does the 8086 push registers on INT 21H?
   A. IP, CS, then FLAGS
   B. FLAGS, then CS, then IP
   C. CS, IP, then FLAGS
   D. FLAGS, IP, then CS
   Answer: B. FLAGS is pushed first, then IF and TF are cleared, then CS and IP. (Key point: Push order)

3. If SP = 1000H before INT 21H, what is SP when the ISR starts?
   A. 0FFAH
   B. 0FFEH
   C. 0FFCH
   D. 1006H
   Answer: A. Three 2-byte pushes reduce SP by 6: 1000H - 6 = 0FFAH. (Key point: Stack pointer)

4. Why are IF and TF cleared when the interrupt is accepted?
   A. To erase the flags permanently
   B. To select the vector table
   C. To stop INTR and single stepping from interrupting the ISR
   D. To enable NMI
   Answer: C. Clearing IF and TF disables INTR and trace; IRET later restores the original flags. (Key point: Why IF/TF cleared)

## Related in Microprocessor

- [ISR, IVT and type 0 to 4 interrupts](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aivt-ir-isr-type-0-to-4) — Microprocessor, chapter 5
- [Interrupt vector table and its use](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aivt-interrupt-handling) — Microprocessor, chapter 5, asked 3×
- [Interrupt processing in 8086](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Ainterrupt-processing-8086) — Microprocessor, chapter 5, asked 3×
- [Sequence of steps when interrupt occurs](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Ainterrupt-occurrence-steps) — Microprocessor, chapter 5, asked 2×
- [8086 ALP: multiplication table of a number](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aalp-8086-multiplication-table) — Microprocessor, chapter 3
- [EI, DI, SIM, RIM and ISR address](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aei-di-sim-rim-vector-address) — Microprocessor, chapter 5

## Related in other subjects

- [IRQ, ISR, IVT, PUSH, POP, latency](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Ainterrupt-terms-irq-isr-ivt) — Embedded System, chapter 5
- [Interrupt and fixed ISR flow of actions](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Ainterrupt-fixed-isr-flow) — Embedded System, chapter 5
- [Instruction cycle state diagram with interrupt](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Ainstr-cycle) — Computer Organization and Architecture, chapter 1, asked 6×