--- title: "Interrupt vector table and its use" subject: "Microprocessor" chapter: 5 key: "semester_4/microprocessor:ivt-interrupt-handling" source: https://www.bctengineer.com/q/semester_4/microprocessor/ivt-interrupt-handling site: BCT Engineering --- # Interrupt vector table and its use Microprocessor · Chapter 5: Interrupt Operations - Asked in: 2072 Magh, 2+6 marks; 2070 Bhadra, 3+5 marks; 2068 Magh, 2+6 marks (asked 3 times) - Video: [Interrupt Vector Table (IVT) in 8086 Microprocessor: Addressing and Details](https://www.youtube.com/watch?v=NtYq-ZeV78U) — Engineering Funda - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_4/microprocessor/ivt-interrupt-handling - Whole chapter: https://www.bctengineer.com/md/semester_4/microprocessor/chapter-5 ## Question What is an Interrupt Vector Table (IVT)? How is it used to handle software and hardware interrupts in microprocessor (8086)? Explain. ## Short answer IVT is a table at 00000H–003FFH storing 4-byte vectors (IP,CS) per interrupt type at address 4×n. For software INT n, CPU pushes flags/CS/IP, loads vector. Hardware NMI uses fixed type 2; INTR gets type from PIC after INTA' and fetches vector similarly. ## Answer #### Interrupt Vector Table (IVT) The IVT is a table in the lowest 1 KB of memory (00000H–003FFH) that stores the starting addresses (vectors) of the 256 interrupt service routines. Each entry is 4 bytes: the 2-byte IP (low byte first) followed by the 2-byte CS. So the entry for interrupt type *n* is at address **4 × n**. | Types | Use | |---|---| | 0 – 4 | Dedicated: divide error, single step, NMI, breakpoint, overflow | | 5 – 31 | Reserved by Intel for future use | | 32 – 255 | Available to the user (software and hardware interrupts) | ```text Address Content 003FCH | Type 255 | ... | ... | 00008H | Type 2 (NMI) | 00004H | Type 1 | 00000H | Type 0 | (each 4-byte entry: IP low, IP high, CS low, CS high) ``` #### Use for software interrupts 1. The program executes **INT n** (opcode CDH, then the type number). INT 3 is the 1-byte opcode CCH, and INTO is CEH. 2. The CPU pushes FLAGS, clears IF and TF, and pushes CS and IP. 3. It calculates 4×n and loads IP and CS from the table. 4. The ISR executes, and **IRET** restores IP, CS and FLAGS. Example: INT 21H → vector at 21H × 4 = 0084H. This is how DOS services are called. #### Use for hardware interrupts - **NMI** has the fixed type 2, so the CPU takes the vector from 00008H. - **INTR**: after the INTA' cycles the interrupt controller (8259A) supplies the type number on the data bus. The CPU multiplies it by 4 and reads the vector in the same way. Different devices give different types, so each can have its own ISR. The programmer or the operating system loads the ISR addresses into the IVT (for example with DOS function 25H) before the interrupt can be used. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. Where is the 8086 interrupt vector table located and how big is it? A. 00000H-003FFH, 1 KB holding 256 four-byte vectors B. FFFF0H-FFFFFH, 16 bytes holding 8 vectors C. 00000H-000FFH, 256 bytes holding 64 four-byte vectors D. 00000H-007FFH, 2 KB holding 256 eight-byte vectors Answer: A. The IVT sits in the lowest 1 KB of memory and has 256 entries of 4 bytes each (IP and CS). (Key point: IVT location and size) 2. Where is the vector for INT 21H stored? A. 0084H (21H x 4) B. 0042H (21H x 2) C. 0021H (same as the type number) D. 0108H (21H x 8) Answer: A. Each entry is 4 bytes, so the vector for type n is at 4 x n; 21H x 4 = 84H. (Key point: Vector address calculation) 3. How is one 4-byte IVT entry arranged? A. CS low, CS high, IP low, IP high B. IP low, IP high, CS low, CS high C. Flags, IP, CS, SP D. IP high, IP low, CS high, CS low Answer: B. The 2-byte IP is stored first (low byte first), followed by the 2-byte CS. (Key point: Vector entry format) 4. Which sequence does the 8086 follow for INT n? A. Push FLAGS, clear IF and TF, push CS and IP, load IP and CS from 4 x n B. Push IP and CS only, then jump to address n C. Clear IF, load CS and IP from the table, then push FLAGS D. Push FLAGS, load IP and CS from 4 x n, then clear IF and TF Answer: A. The CPU saves FLAGS, CS and IP, disables INTR and single stepping, then fetches the new CS:IP from the table. (Key point: Software interrupt sequence) ## Related in Microprocessor - [Hardware interrupts available in 8086](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3A8086-hardware-interrupts) — Microprocessor, chapter 5 - [Hardware vs software interrupts](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Ahardware-vs-software-interrupts) — Microprocessor, chapter 5 - [ISR, IVT and type 0 to 4 interrupts](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aivt-ir-isr-type-0-to-4) — Microprocessor, chapter 5 - [IVT in 8086 and ISR execution sequence](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aivt-8086-isr-execution-sequence) — Microprocessor, chapter 5 - [Interrupt processing in 8086](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Ainterrupt-processing-8086) — Microprocessor, chapter 5, asked 3× - [Software interrupts of 8085](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3A8085-software-interrupts) — Microprocessor, chapter 5 ## Related in other subjects - [How interrupts interface with microprocessor](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Ainterrupt-interface-microprocessor) — Embedded System, chapter 5 - [Audio hardware and audio software](https://www.bctengineer.com/question.md?key=semester_8%2Fmultimedia_system%3Aaudio-hardware-software) — Multimedia System, chapter 2 - [Software used for FEM and FDM](https://www.bctengineer.com/question.md?key=semester_8%2Fcomputational_techniques_in_civil_engineering%3Asoftware-fem-fdm) — Computational Techniques in Civil Engineering, chapter 1 - [IRQ, ISR, IVT, PUSH, POP, latency](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Ainterrupt-terms-irq-isr-ivt) — Embedded System, chapter 5