---
title: "Machine cycle, T-states, ANI 55H timing"
subject: "Microprocessor"
chapter: 2
key: "semester_4/microprocessor:machine-cycle-tstate-ani-55h"
source: https://www.bctengineer.com/q/semester_4/microprocessor/machine-cycle-tstate-ani-55h
site: BCT Engineering
---

# Machine cycle, T-states, ANI 55H timing

Microprocessor · Chapter 2: Programming with 8085 Microprocessor

- Asked in: 2074 Bhadra, 2+5+1 marks
- Video: [TRICKS TO MAKE TIMING DIAGRAM IN MICROPROCESSOR](https://www.youtube.com/watch?v=TQbiUsM_r6A) — TECHNOSHAPIONS EDUCATIONS
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_4/microprocessor/machine-cycle-tstate-ani-55h
- Whole chapter: https://www.bctengineer.com/md/semester_4/microprocessor/chapter-2

## Question

What do you mean by Machine cycle and T-states? Draw a bus timing diagram for an instruction ANI 55H of 8085 microprocessor. Calculate the time required to execute such instruction, if microprocessor is operating at 2 MHz clock frequency.

## Short answer

A machine cycle is the time for one memory or I/O operation (3–6 T-states); a T-state is one clock period. ANI 55H requires opcode fetch (4T) and memory read (3T) = 7 T-states. At 2 MHz, T = 0.5 µs, so execution time = 3.5 µs.

## Answer

#### Machine cycle
A **machine cycle** is the time needed to complete one basic memory or I/O operation: opcode fetch, memory read, memory write, I/O read or I/O write. It consists of 3 to 6 T-states.

#### T-state
A **T-state** is one clock period of the processor clock; it is the smallest unit of time (T = 1 / f). An instruction cycle is made of several machine cycles, and each machine cycle of several T-states.

#### Timing diagram of ANI 55H
`ANI 55H` (opcode E6H, data 55H) is a 2-byte instruction: M1 opcode fetch (4T) and M2 memory read (3T) = 7 T-states. Assume it is stored at 2000H.

| M-cycle | T | A15-A8 | AD7-AD0 | ALE | Control | IO/M S1 S0 |
|---|---|---|---|---|---|---|
| **M1 (opcode fetch, 4T)** | T1 | 20H | 00H (PCL) | 1 | - | 0 1 1 |
|  | T2 | 20H | Hi-Z (bus floats) | 0 | RD low | 0 1 1 |
|  | T3 | 20H | E6H (opcode in) | 0 | RD low, rises at end | 0 1 1 |
|  | T4 | - | - | 0 | none (decode) | 0 1 1 |
| **M2 (memory read, 3T)** | T1 | 20H | 01H | 1 | - | 0 1 0 |
|  | T2 | 20H | Hi-Z (bus floats) | 0 | RD low | 0 1 0 |
|  | T3 | 20H | 55H (data in) | 0 | RD low, rises at end | 0 1 0 |

```text
      |  M1 (OF)  | M2 (MR) |
      |T1 T2 T3 T4|T1 T2 T3 |
 ALE  |HI lo lo lo|HI lo lo |
 RD   |hi LO LO hi|hi LO LO |
 WR   |hi hi hi hi|hi hi hi |
```
M1 reads E6H from 2000H, M2 reads 55H from 2001H. The AND operation is done after the data byte is received.

#### Execution time
Clock frequency f = 2 MHz, so T = 1 / 2 MHz = 0.5 microsecond.

Time = 7 x 0.5 microsecond = **3.5 microseconds**.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. Which is the correct definition of a machine cycle?
   A. One period of the processor clock
   B. The time needed to complete one basic memory or I/O operation, made of 3 to 6 T-states
   C. The time needed to fetch and execute a whole instruction
   D. The time needed to decode an opcode in T4
   Answer: B. A machine cycle is one basic operation such as opcode fetch or memory read and lasts 3 to 6 T-states; a whole instruction is an instruction cycle. (Key point: Machine cycle = one basic memory/I-O operation of 3 to 6 T-states)

2. What is a T-state?
   A. One clock period of the processor, the smallest unit of time (T = 1/f)
   B. One complete opcode fetch cycle
   C. The time for which ALE stays high
   D. A group of machine cycles
   Answer: A. A T-state is one clock period; machine cycles are made of several T-states, and instruction cycles of several machine cycles. (Key point: T-state = one clock period (T = 1/f), the smallest unit of time)

3. Which machine cycles does ANI 55H need?
   A. Opcode fetch only (4T), because ANI is a logical instruction
   B. Opcode fetch (4T) and memory write (3T) = 7T
   C. Opcode fetch (4T), memory read (3T), memory read (3T) = 10T
   D. Opcode fetch (4T) and memory read (3T) = 7T
   Answer: D. ANI 55H is a 2-byte instruction: M1 fetches opcode E6H and M2 reads the data byte 55H from the next location, for 7 T-states. (Key point: ANI 55H is 2 bytes: opcode fetch (4T) + memory read (3T) = 7T)

4. If the 8085 operates at a 2 MHz clock, how long does ANI 55H take?
   A. 7 x 1 microsecond = 7 microseconds
   B. 4 x 0.5 microsecond = 2 microseconds
   C. 7 x 0.5 microsecond = 3.5 microseconds
   D. 7 x 0.25 microsecond = 1.75 microseconds
   Answer: C. The operating clock is given as 2 MHz, so T = 1/2 MHz = 0.5 microsecond, and 7 T-states take 3.5 microseconds. (Key point: At 2 MHz, T = 0.5 microsecond, so 7T = 3.5 microseconds)

## Related in Microprocessor

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