---
title: "Maskable vs non-maskable interrupts"
subject: "Microprocessor"
chapter: 5
key: "semester_4/microprocessor:maskable-vs-nonmaskable"
source: https://www.bctengineer.com/q/semester_4/microprocessor/maskable-vs-nonmaskable
site: BCT Engineering
---

# Maskable vs non-maskable interrupts

Microprocessor · Chapter 5: Interrupt Operations

- Asked in: 2073 Bhadra, 2 marks; 2070 Magh, 2 marks (asked 2 times)
- Video: [Interrupts in 8085|Hardware & software interrupts|maskable & non maskable interrupts|Microprocessor](https://www.youtube.com/watch?v=nQE6xfAcdys) — Slate and Pencil
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_4/microprocessor/maskable-vs-nonmaskable
- Whole chapter: https://www.bctengineer.com/md/semester_4/microprocessor/chapter-5

## Question

Differentiate between maskable and non-maskable interrupts.

## Short answer

Maskable interrupts (8086 INTR, 8085 RST 5.5–7.5) can be disabled by clearing IF or setting mask bits; lower priority, used for I/O. Non-maskable (8086 NMI, 8085 TRAP) cannot be disabled by software, have highest priority, used for emergencies like power failure.

## Answer

| Basis | Maskable interrupt | Non-maskable interrupt |
|---|---|---|
| Meaning | Can be disabled (ignored) by software | Cannot be disabled by software |
| Control | Controlled by the interrupt flag (IF); DI/CLI disables, EI/STI enables | Not affected by IF |
| Priority | Lower | Highest |
| Typical use | Normal I/O devices (keyboard, printer) | Emergencies: power failure, memory parity error |
| 8085 / 8086 | 8085: RST 7.5, 6.5, 5.5, INTR; 8086: INTR | 8085: TRAP; 8086: NMI |
| Vector | Fixed for 8085 RST 7.5/6.5/5.5; for INTR it is supplied by the device or controller | Fixed (TRAP 0024H; NMI type 2) |

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. What makes an interrupt maskable?
   A. Software can disable it, e.g. using the interrupt flag
   B. It has a fixed vector address
   C. It always has the highest priority
   D. It is generated only by an instruction
   Answer: A. A maskable interrupt can be ignored by software, controlled by IF through DI/EI or CLI/STI. (Key point: Definition of maskable)

2. Which event is typically handled by a non-maskable interrupt?
   A. Keyboard key press
   B. Printer ready signal
   C. Power failure or memory parity error
   D. Normal disk transfer
   Answer: C. Emergencies that need immediate attention use the non-maskable interrupt; normal I/O uses maskable ones. (Key point: Typical use of NMI)

3. Which pair lists the non-maskable interrupts of the 8085 and 8086 respectively?
   A. INTR and NMI
   B. TRAP and NMI
   C. RST 7.5 and INTR
   D. TRAP and INTR
   Answer: B. TRAP is non-maskable in the 8085 and NMI is non-maskable in the 8086. (Key point: 8085/8086 examples)

## Related in Microprocessor

- [Hardware vs software interrupts](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Ahardware-vs-software-interrupts) — Microprocessor, chapter 5
- [Interrupt vs polling; interrupts in 8085](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Ainterrupt-vs-polling-8085) — Microprocessor, chapter 5

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