---
title: "Memory capacity from range and interfacing"
subject: "Microprocessor"
chapter: 4
key: "semester_4/microprocessor:memory-range-capacity-interfacing"
source: https://www.bctengineer.com/q/semester_4/microprocessor/memory-range-capacity-interfacing
site: BCT Engineering
---

# Memory capacity from range and interfacing

Microprocessor · Chapter 4: Microprocessor System

- Asked in: 2071 Magh, 2+6 marks
- Video: [How to calculate Memory Range Problem with solution microprocessor 8085 memory mapped I/O gate](https://www.youtube.com/watch?v=Erj5jMVfH7s) — Engineer Tree
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_4/microprocessor/memory-range-capacity-interfacing
- Whole chapter: https://www.bctengineer.com/md/semester_4/microprocessor/chapter-4

## Question

Determine the capacity of devices in the following memory range.
| Range | Device |
|---|---|
| 0000-1FFF | ROM |
| 2000-3FFF | RAM1 |
Design an interfacing circuit to interface above memory devices with 8085 microprocessor.

## Short answer

ROM capacity: 2000H bytes = 8KB (0000H–1FFFH). RAM1 capacity: 2000H bytes = 8KB (2000H–3FFFH). Interface: decode A15–A13 with 74LS138 (C,B,A = A15,A14,A13, G1=+5V, G2B'=GND, G2A'=IO/M'), Y0' to ROM CE', Y1' to RAM CS'. Both 8KB chips use A12–A0, RD' to OE', WR' to WE' of RAM, common data bus.

## Answer

#### Capacity of the devices

Capacity = (end address − start address) + 1.

- ROM: 1FFFH − 0000H + 1 = 2000H = 2¹³ = 8192 locations = **8K×8 (8 KB)**; it needs 13 address lines A12–A0.
- RAM1: 3FFFH − 2000H + 1 = 2000H = 8192 locations = **8K×8 (8 KB)**; it also needs A12–A0.

#### Address decoding

| Device | Range | A15 A14 A13 |
|---|---|---|
| ROM | 0000H – 1FFFH | 0 0 0 |
| RAM1 | 2000H – 3FFFH | 0 0 1 |

A12–A0 vary inside each chip. Only A15, A14, A13 (and IO/M') are decoded.

#### Interfacing circuit (74LS138)

- C, B, A = A15, A14, A13. 000 → Y0' (ROM); 001 → Y1' (RAM1).
- G1 = +5 V, G2B' = GND, G2A' = IO/M' (memory cycle only).
- Y0' → CE' of ROM; Y1' → CS' of RAM1.
- A12–A0 → address pins of both chips.
- RD' → OE' of ROM and RAM1; WR' → WE' of RAM1 only.
- D7–D0 (AD7–AD0) connect to the data pins of both chips.

```text
 A15 -- C \
 A14 -- B  | 74LS138     +--------+
 A13 -- A /   Y0' ------ |CE' ROM | 0000-1FFF
 IO/M' - G2A' Y1' --+    |8K x 8  |
 GND --- G2B'       |    +--------+
 +5V --- G1         |    +--------+
                    +----|CS' RAM1| 2000-3FFF
                         |8K x 8  |
 A12-A0 -> both;  RD'->OE';  WR'->WE' (RAM)
```

The lower address byte is multiplexed with data on AD7–AD0, so a 74LS373 latch enabled by ALE is first used to separate A7–A0. A15–A8 are available directly. Signals marked with a prime (RD', WR', IO/M', CE', OE') are active low.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. What is the capacity of the ROM at 0000-1FFF?
   A. 4K x 8
   B. 8K x 8 (8192 locations)
   C. 16K x 8
   D. 2K x 8
   Answer: B. 1FFFH - 0000H + 1 = 2000H = 8192 locations = 8 KB, needing 13 address lines. (Key point: Capacity result)

2. What is the formula used to find capacity from a range?
   A. End address minus start address
   B. Start address plus end address
   C. (End address - start address) + 1
   D. End address divided by 2
   Answer: C. Both end and start addresses are included, so the count of locations is end minus start plus 1. (Key point: Capacity formula)

3. Which pattern and output select RAM1 (2000H-3FFFH)?
   A. A15A14A13 = 001, Y1'
   B. A15A14A13 = 000, Y0'
   C. A15A14A13 = 010, Y2'
   D. A15A14A13 = 011, Y3'
   Answer: A. 2000H = 0010 0000..., so A15A14A13 = 001 which is Y1'. (Key point: RAM1 selection)

4. How are the read and write signals connected?
   A. WR' to WE' of both chips
   B. RD' to OE' of the ROM only
   C. WR' to CE' of the ROM
   D. RD' to OE' of both, but WR' to WE' of RAM1 only
   Answer: D. ROM cannot be written, so only the RAM receives WR' on WE'. (Key point: Write connection)

## Related in Microprocessor

- [74LS138 interfacing of ROM, RAM, EPROM](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-74ls138-rom-ram-eprom) — Microprocessor, chapter 4
- [Interface two 8K x 8 ROM at 4000H](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-two-8k-rom-4000h) — Microprocessor, chapter 4
- [Interface two 4K x 8 ROM with 3:8 decoder](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-two-4k-rom-38-decoder) — Microprocessor, chapter 4
- [Interfacing 2732 EPROM and 6116 RAM](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-74ls138-2732-6116) — Microprocessor, chapter 4
- [Interface 4 KB EPROM and two 2 KB RAM](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Ainterface-4kb-eprom-two-2kb-ram) — Microprocessor, chapter 4
- [8085 ALP: copy data within a range](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aalp-8085-copy-range) — Microprocessor, chapter 2

## Related in other subjects

- [Memory-mapped I/O design for 8085](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Amemmapped-io-design-1000h) — Instrumentation II, chapter 2
- [Interfacing ADC0808 with 8085 using 8255A](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aadc0808-8255-interface) — Instrumentation II, chapter 4
- [8-channel ADC interface with 8255 and 8085](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aadc8-8255-problem) — Instrumentation II, chapter 4
- [Interfacing: 512-byte RAM with 8085](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Arag-ram-512-interface) — Instrumentation II, chapter 2