--- title: "Microprocessor based system and bus organization" subject: "Microprocessor" chapter: 1 key: "semester_4/microprocessor:mp-based-system-bus-organization" source: https://www.bctengineer.com/q/semester_4/microprocessor/mp-based-system-bus-organization site: BCT Engineering --- # Microprocessor based system and bus organization Microprocessor · Chapter 1: Introduction to Microprocessor - Asked in: 2073 Magh, 4 marks; 2072 Magh, 4 marks; 2071 Bhadra, 4 marks; 2069 Bhadra, 2+6 marks; 2068 Magh, 8 marks (asked 5 times) - Video: [micro processor based system | MPMC | Lec-09 | Bhanu Priya](https://www.youtube.com/watch?v=IxVycaJB9Ok) — Education 4u - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_4/microprocessor/mp-based-system-bus-organization - Whole chapter: https://www.bctengineer.com/md/semester_4/microprocessor/chapter-1 ## Question Explain the microprocessor based system (draw the block diagram and explain each part), showing the bus organization. ## Short answer A microprocessor-based system has a CPU, ROM for permanent programs, RAM for user data, and I/O interfaces, all linked by three buses: the address bus selects a location, the bidirectional data bus transfers information, and the control bus supplies read/write, timing, and interrupt signals. The CPU fetches and executes stored programs using these buses. ## Answer A **microprocessor based system** is a computer system built around a microprocessor (CPU) together with memory and input/output devices, all connected by buses. ```text +-------+ | Clock | +---+---+ | +---+---+ +--------+ +--------+ +--------+ | CPU | | ROM | | RAM | | I/O | | (MPU) | | | | | | devices| +---+---+ +---+----+ +---+----+ +---+----+ | | chip select | | | +---+----------------+------------+---+ | | Address decoder | | +-----------------+-------------------+ | | ====+=========================+===================== Address bus ====+============================================== Data bus ====+============================================== Control bus (ROM, RAM and I/O also connect to all three buses) ``` #### Parts of the system - **Microprocessor (CPU)**: the brain. It has the ALU (arithmetic and logic operations), registers (temporary storage), and the control unit (fetches, decodes and generates timing/control signals). - **Memory**: stores programs and data. **ROM** holds permanent programs (e.g., boot/monitor program) and is non-volatile. **RAM** holds the user program and data being processed and is volatile. - **Input/Output devices**: connect the system to the outside world. Input devices (keyboard, switches, sensors) send data in; output devices (display, printer, LEDs) take data out. They are connected through interface chips (ports) such as 8255. - **Buses**: groups of wires that carry information between the parts. #### Bus organization 1. **Address bus**: unidirectional; carries the address of the memory location or I/O port from the CPU. An *n*-bit address bus can address 2ⁿ locations (8085: 16 lines, 64 KB). 2. **Data bus**: bidirectional; carries data between CPU, memory and I/O. Its width (8 bits in 8085) gives the word length. 3. **Control bus**: carries control and timing signals such as RD, WR, IO/M, ALE, INTR, HOLD, READY, so that only the selected device responds and data flows in the right direction at the right time. On the 8085 the lower address lines are multiplexed with the data bus (AD0-AD7). In T1 of each machine cycle the CPU puts the low address byte on AD0-AD7 and raises **ALE**; an external latch (e.g. 74LS373) holds it as A0-A7. From T2 the same lines carry data. A8-A15 carry the high address byte throughout. When a device such as a DMA controller raises **HOLD**, the CPU finishes its current cycle, answers with **HLDA** and tri-states its buses so the other device can use them. The CPU puts an address on the address bus; the address decoder selects one device; the control bus tells whether to read or write; and data moves on the data bus. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. Which statement about the address bus is correct? A. Bidirectional, carries data B. Unidirectional from CPU; n lines address 2^n locations C. Unidirectional into the CPU; carries RD and WR D. Bidirectional; n lines address n^2 locations Answer: B. The address bus is one-way from the CPU, and n lines select 2^n locations (16 lines = 64 KB in 8085). (Key point: Address bus) 2. What does the width of the data bus decide? A. The number of memory locations B. The clock speed C. The word length D. The number of I/O ports Answer: C. Data bus width (8 bits in 8085) gives the word length. (Key point: Data bus) 3. How does the 8085 separate the low address byte from data on AD0-AD7? A. ALE goes high in T1 and an external latch holds the low address byte B. HOLD goes high and the lines are tri-stated C. RD goes low in T1 to latch the address D. The address decoder stores it Answer: A. In T1 the CPU puts A0-A7 on AD0-AD7 and raises ALE; a latch like 74LS373 holds it, then the lines carry data. (Key point: Multiplexed AD0-AD7) 4. What happens when a DMA controller raises HOLD? A. CPU aborts the instruction and resets B. CPU finishes the current cycle, sends HLDA and tri-states its buses C. CPU keeps using the buses and ignores it D. CPU switches to the interrupt cycle Answer: B. The CPU completes its cycle, answers HLDA and floats its buses so the other device can use them. (Key point: HOLD/HLDA) ## Related in Microprocessor - [Bus organization and memory capacity](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Abus-organization-memory-capacity) — Microprocessor, chapter 1 - [Accumulator based and register based architecture](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aaccumulator-register-based-architecture) — Microprocessor, chapter 6, asked 2× - [Synchronous/asynchronous bus; LXI timing](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Async-async-bus-lxi-timing) — Microprocessor, chapter 2, asked 2× - [Timing diagram of STA 8050H](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Atiming-sta-8050h) — Microprocessor, chapter 2 - [Bus, bus types and RTL for MOV](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Abus-types-rtl-mov) — Microprocessor, chapter 1 - [Bus timing of OUT 42H](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Atiming-out-42h) — Microprocessor, chapter 2 ## Related in other subjects - [Microprocessor-based transmission line protection](https://www.bctengineer.com/question.md?key=semester_6%2Fswitchgear_and_protection%3Amicroprocessor-line-protection) — Switchgear and Protection, chapter 8, asked 2× - [General block diagram of a control system](https://www.bctengineer.com/question.md?key=semester_3%2Fcontrol_systems%3Ageneral-bd-control-system) — Control Systems, chapter 1 - [Features of microprocessor based instrumentation](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Ambi-features) — Instrumentation II, chapter 1, asked 4× - [Types of microprocessor based instrumentation systems](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Ambi-types) — Instrumentation II, chapter 1