--- title: "Modes of parallel data transfer" subject: "Microprocessor" chapter: 4 key: "semester_4/microprocessor:parallel-data-transfer-modes" source: https://www.bctengineer.com/q/semester_4/microprocessor/parallel-data-transfer-modes site: BCT Engineering --- # Modes of parallel data transfer Microprocessor · Chapter 4: Microprocessor System - Asked in: 2072 Asoj, 4 marks - Video: [Modes of parallel data transfer | parallel interface modes](https://www.youtube.com/watch?v=FMUQ3FhWw1k) — hercules channel - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_4/microprocessor/parallel-data-transfer-modes - Whole chapter: https://www.bctengineer.com/md/semester_4/microprocessor/chapter-4 ## Question Explain different modes of parallel data transfer. ## Short answer Parallel transfer modes include simple unconditional I/O, strobed I/O with status or strobe, single handshake using one control line, and double handshake using DAV and ACK for reliable transfer. Interrupt-driven I/O and DMA are also used at system level. ## Answer In parallel I/O, all data bits are sent together. The method used to synchronise the processor with the peripheral gives the following modes. 1. **Simple (unconditional) I/O:** the processor sends or reads data whenever it wants, assuming the device is always ready (e.g. LEDs, switches). No control signals are used. This is 8255 mode 0. 2. **Strobed (conditional) I/O:** the processor first checks the device status (polling), or the device signals with a strobe that the data is valid, and only then is the data transferred. Used for keyboards. 3. **Single handshake:** one control line from the sender (strobe/DAV) says "data valid"; the receiver takes the data but sends no acknowledge. Suitable when the receiver is always fast enough. 4. **Double handshake (interlocked):** two lines are used: the sender puts out the data and asserts DAV; the receiver accepts the data and returns ACK; the sender then removes DAV and the receiver removes ACK. Reliable for devices of different speeds (8255 modes 1 and 2). **Other transfer methods at system level** - **Interrupt-driven I/O:** the device interrupts the processor when it is ready. - **DMA:** a DMA controller transfers data directly between the device and memory. ```text Handshake: data ====valid======= DAV ___|‾‾‾‾‾‾‾‾|______ ACK _____|‾‾‾‾‾‾‾‾|____ ``` ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What characterises simple (unconditional) I/O? A. The device must give an ACK B. The processor polls a status line first C. The processor transfers data at any time, assuming the device is always ready D. It needs a double handshake Answer: C. Simple I/O has no control signals; it is used for LEDs and switches and corresponds to 8255 mode 0. (Key point: Simple I/O) 2. What is the key feature of single handshake? A. Only a strobe/DAV from the sender; the receiver sends no acknowledge B. The receiver sends ACK after reading C. Two lines are used D. The sender waits for the receiver to remove ACK Answer: A. Single handshake uses one control line (data valid) and gives no acknowledgement, so it suits receivers that are always fast enough. (Key point: Single handshake) 3. In double (interlocked) handshake, what does the sender do after the receiver returns ACK? A. Sends the next byte at once B. Removes DAV, and then the receiver removes ACK C. Keeps DAV active D. Sends a second strobe Answer: B. The sender sees ACK, removes DAV, and the receiver then removes ACK, completing the cycle. (Key point: Double handshake sequence) 4. How does interrupt-driven I/O differ from polling? A. The CPU checks the device status in a loop B. A DMA controller moves the data C. The device sends no signal D. The device interrupts the processor when it is ready Answer: D. In interrupt-driven I/O the device signals the CPU when ready, so the CPU does not wait in a polling loop. (Key point: Interrupt-driven I/O) ## Related in Microprocessor - [Instruction and data format, addressing modes](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3A8085-instruction-data-format-addressing) — Microprocessor, chapter 2, asked 2× - [8085 ALP: transfer data with more than 3 ones](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aalp-8085-ones-greater-than-3) — Microprocessor, chapter 2 - [8085 ALP: odd parity transfer with bit change](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aalp-8085-odd-parity-transfer) — Microprocessor, chapter 2 ## Related in other subjects - [Modes of heat transfer with rate equations](https://www.bctengineer.com/question.md?key=semester_5%2Fheat_transfer%3Amodes-of-heat-transfer) — Heat Transfer, chapter 1 - [Parallel transfer schemes and 8255A block diagram](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aparallel-transfer-8255-block) — Instrumentation II, chapter 2 - [Why serial transfer is preferred over parallel](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aserial-vs-parallel-preferred) — Instrumentation II, chapter 3 - [Data file and file modes](https://www.bctengineer.com/question.md?key=semester_1%2Fcomputer_programming%3Adata-file-modes) — Computer Programming, chapter 10