--- title: "PC and SP in CALL, RET, PUSH, POP" subject: "Microprocessor" chapter: 2 key: "semester_4/microprocessor:pc-sp-call-ret-push-pop" source: https://www.bctengineer.com/q/semester_4/microprocessor/pc-sp-call-ret-push-pop site: BCT Engineering --- # PC and SP in CALL, RET, PUSH, POP Microprocessor · Chapter 2: Programming with 8085 Microprocessor - Asked in: 2074 Bhadra, 4+4 marks - Video: [Stack Pointer in 8085 Microprocessor Explained in Hindi](https://www.youtube.com/watch?v=X-8H9cwYgW0) — 5 Minutes Engineering - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_4/microprocessor/pc-sp-call-ret-push-pop - Whole chapter: https://www.bctengineer.com/md/semester_4/microprocessor/chapter-2 ## Question What is the use of Program Counter and Stack Pointer registers of 8085 microprocessor? How these registers get affected during CALL, RET, PUSH and POP instructions explain with suitable examples. ## Short answer PC holds the address of the next instruction; SP points to the top of stack. CALL pushes the return address and loads the subroutine address, decreasing SP by 2; RET pops it, increasing SP by 2. PUSH decrements SP and stores a register pair; POP loads a pair and increments SP. ## Answer #### Program Counter (PC) A 16-bit register that holds the address of the next instruction to be fetched. It is incremented automatically after each byte fetched, so instructions execute in sequence. Jump, call and return load a new address into it. #### Stack Pointer (SP) A 16-bit register that holds the address of the top of the stack, a LIFO region of RAM used to save return addresses and register contents. In the 8085 the stack grows downward: SP is decremented on a push and incremented on a pop. It is initialised with `LXI SP,addr`. #### Effect on PC and SP **CALL addr (3 bytes, 18T)**: Suppose `CALL 4000H` is at 2000H, SP = 3FFFH. ```text Before: PC = 2000H SP = 3FFFH Fetch bytes: PC = 2003H (next instruction address) SP-1 = 3FFEH <- PCH = 20H SP-2 = 3FFDH <- PCL = 03H After: SP = 3FFDH PC = 4000H ``` The return address is pushed on the stack, SP decreases by 2, and PC gets the subroutine address. **RET (1 byte, 10T)**: ```text PCL <- M[SP] = 03H ; PCH <- M[SP+1] = 20H SP <- SP + 2 = 3FFFH After: PC = 2003H ``` SP increases by 2 and PC returns to the instruction after the CALL. **PUSH B** (stores BC; 12T): PC increases only by 1 (fetching the opcode); SP changes. ```text Before: B = 12H, C = 34H, SP = 3FFFH M[SP-1] = 3FFEH <- B = 12H M[SP-2] = 3FFDH <- C = 34H After: SP = 3FFDH ``` **POP D** (loads DE; 10T): ```text E <- M[SP] ; D <- M[SP+1] ; SP <- SP + 2 ``` If M[3FFDH] = 34H and M[3FFEH] = 12H: E = 34H, D = 12H, SP = 3FFFH. PUSH/POP do not change the PC except for its normal increment, while CALL and RET load PC with a new value as well as using the stack. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. Which pair of statements about PC and SP in the 8085 is correct? A. PC holds the current instruction's opcode; SP is incremented on PUSH B. PC holds the address of the next instruction to fetch; SP holds the top-of-stack address and is decremented on PUSH C. PC is an 8-bit register; SP is a 16-bit register that grows upward D. PC holds the address of the top of the stack; SP holds the next instruction address Answer: B. PC is a 16-bit register pointing to the next instruction to fetch. SP is a 16-bit register pointing to the top of the stack; the 8085 stack grows downward, so SP decreases on a push. (Key point: PC holds the address of the next instruction; SP points to the top of a downward-growing stack) 2. CALL 4000H is at address 2000H and SP = 3FFFH. What are PC and SP after it executes, and what is stored at 3FFEH and 3FFDH? A. PC = 4000H, SP = 4001H; 3FFEH = 20H, 3FFDH = 00H B. PC = 2003H, SP = 3FFDH; 3FFEH = 40H, 3FFDH = 00H C. PC = 4000H, SP = 3FFDH; 3FFEH = 20H (PCH), 3FFDH = 03H (PCL) D. PC = 4000H, SP = 3FFDH; 3FFEH = 03H (PCL), 3FFDH = 20H (PCH) Answer: C. The return address 2003H (the instruction after the 3-byte CALL) is pushed, with PCH at SP-1 and PCL at SP-2, so SP becomes 3FFDH. PC is then loaded with 4000H. (Key point: CALL pushes the return address (PC after CALL) and loads PC with the target) 3. After the CALL above, the subroutine executes RET with SP = 3FFDH. What happens? A. PCH <- M[3FFDH], PCL <- M[3FFEH], SP = 3FFBH B. PC <- 4000H and SP is unchanged C. PCL <- M[3FFDH], PCH <- M[3FFEH], SP = 3FFEH D. PCL <- M[3FFDH] = 03H, PCH <- M[3FFEH] = 20H, SP = 3FFFH, PC = 2003H Answer: D. RET loads PCL from M[SP] and PCH from M[SP+1], then SP increases by 2. PC becomes 2003H, the instruction after the CALL. (Key point: RET pops PCL then PCH and adds 2 to SP) 4. How do PUSH B and POP D differ from CALL and RET in their effect on the PC? A. PUSH/POP only increment PC normally (1-byte opcode fetch); CALL/RET load PC with a new value B. PUSH/POP load PC from the stack, just like RET C. PUSH/POP do not change SP; only CALL/RET change SP D. PUSH increments PC by 2 and POP decrements PC by 2 Answer: A. PUSH and POP save or restore register pairs through the stack (SP changes by 2), but PC only moves to the next instruction. CALL and RET also use the stack but load a new value into PC. (Key point: PUSH/POP change SP by 2 but PC only increments normally) ## Related in Microprocessor - [Compare CALL/RET with PUSH/POP](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Acall-ret-vs-push-pop) — Microprocessor, chapter 2 - [Classification of 8085 instructions](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3A8085-instruction-classification) — Microprocessor, chapter 2 - [RST instructions in 8085](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Arst-instructions) — Microprocessor, chapter 2 ## Related in other subjects - [Push and pop on stack as linked list](https://www.bctengineer.com/question.md?key=semester_4%2Fdata_structure_and_algorithm%3Astack-push-pop-linked-list) — Data Structure and Algorithm, chapter 4 - [IRQ, ISR, IVT, PUSH, POP, latency](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Ainterrupt-terms-irq-isr-ivt) — Embedded System, chapter 5