---
title: "RTL for LXI instruction"
subject: "Microprocessor"
chapter: 1
key: "semester_4/microprocessor:rtl-lxi-instruction"
source: https://www.bctengineer.com/q/semester_4/microprocessor/rtl-lxi-instruction
site: BCT Engineering
---

# RTL for LXI instruction

Microprocessor · Chapter 1: Introduction to Microprocessor

- Asked in: 2075 Baisakh, 4 marks; 2073 Bhadra, 4 marks; 2070 Magh, 4 marks (asked 3 times)
- Video: [LXI instruction of 8085 microprocessor (LXI B, LXI D, LXI H, LXI SP)](https://www.youtube.com/watch?v=sZN33iN2wQE) — m.laxmikant
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_4/microprocessor/rtl-lxi-instruction
- Whole chapter: https://www.bctengineer.com/md/semester_4/microprocessor/chapter-1

## Question

Write the RTL for the instruction LXI H,75H in 8085 microprocessor. (Explain RTL based on an 8085 instruction; fetch and execution steps.)

## Short answer

LXI H,75H loads HL with 0075H in three machine cycles. Fetch: IR←M[PC], PC+1; then low-byte read: L←M[PC], PC+1 (L = 75H); and high-byte read: H←M[PC], PC+1 (H = 00H). RTL describes these register transfers explicitly.

## Answer

**Register Transfer Language (RTL)** describes the operation of a processor as transfers of data between registers, using symbols: `<-` for transfer, `[ ]` for memory contents, `MAR`, `MDR`, `PC`, `IR` as registers.

`LXI H,75H` loads the 16-bit value 0075H into the HL pair: L gets 75H, H gets 00H. It is a 3-byte instruction (opcode 21H, 75H, 00H), taking 3 machine cycles (10 T-states). Assume it is stored from address X.

#### Machine cycle 1: opcode fetch (T1-T4)
```text
T1: MAR <- PC
T2: MDR <- M[MAR] ;  PC <- PC + 1
T3: IR  <- MDR
T4: decode IR (opcode 21H = LXI H)
```

#### Machine cycle 2: memory read (low-order operand)
```text
T1: MAR <- PC
T2: MDR <- M[MAR] ;  PC <- PC + 1
T3: L   <- MDR            (L = 75H)
```

#### Machine cycle 3: memory read (high-order operand)
```text
T1: MAR <- PC
T2: MDR <- M[MAR] ;  PC <- PC + 1
T3: H   <- MDR            (H = 00H)
```

**Result:** HL = 0075H and PC points to the next instruction (X + 3). The first cycle is the *fetch* phase; the second and third cycles are the *execution* phase (reading the operand).

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. What does LXI H,75H do?
   A. Loads H with 75H and L with 00H
   B. Loads L with 75H and H with 00H
   C. Loads memory 75H into HL
   D. Adds 75H to HL
   Answer: B. It loads 0075H into HL: low byte 75H into L, high byte 00H into H. (Key point: LXI H,75H effect)

2. How many machine cycles and bytes does LXI H,75H have?
   A. 1 cycle, 1 byte
   B. 2 cycles, 2 bytes
   C. 3 cycles, 3 bytes
   D. 4 cycles, 3 bytes
   Answer: C. It is 3 bytes (21H, 75H, 00H) and takes 3 machine cycles: opcode fetch and two memory reads. (Key point: Machine cycles)

3. Which RTL pair belongs to the opcode fetch?
   A. L <- MDR ; H <- MDR
   B. MAR <- PC, MDR <- M[MAR] with PC <- PC+1, IR <- MDR
   C. HL <- 0075H directly in T1
   D. SP <- PC
   Answer: B. Fetch is MAR<-PC, MDR<-M[MAR] with PC<-PC+1, then IR<-MDR. (Key point: Fetch RTL)

## Related in Microprocessor

- [Fetch and execution cycle with RTL](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Afetch-execute-cycle-rtl) — Microprocessor, chapter 1
- [RIM instruction in 8085](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3A8085-rim) — Microprocessor, chapter 5
- [Microprocessor based system and bus organization](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Amp-based-system-bus-organization) — Microprocessor, chapter 1, asked 5×
- [Timing diagram of LXI D, 2465H](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Atiming-lxi-d-2465h) — Microprocessor, chapter 2, asked 2×
- [Execution of ANI 4BH with timing](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Atiming-ani-4bh) — Microprocessor, chapter 2
- [Bus, bus types and RTL for MOV](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Abus-types-rtl-mov) — Microprocessor, chapter 1

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