---
title: "Short note: DMA controller"
subject: "Microprocessor"
chapter: 4
key: "semester_4/microprocessor:short-note-dma"
source: https://www.bctengineer.com/q/semester_4/microprocessor/short-note-dma
site: BCT Engineering
---

# Short note: DMA controller

Microprocessor · Chapter 4: Microprocessor System

- Asked in: 2075 Baisakh, 4 marks; 2074 Bhadra, 4 marks; 2072 Asoj, 4 marks; 2071 Magh, 4 marks (asked 4 times)
- Video: [DMA controller  | Basic operation | MPMC  | Lec-48 | Bhanu Priya](https://www.youtube.com/watch?v=ltvpkuQRZao) — Education 4u
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_4/microprocessor/short-note-dma
- Whole chapter: https://www.bctengineer.com/md/semester_4/microprocessor/chapter-4

## Question

Write a short note on DMA controller.

## Short answer

DMA allows direct data transfer between I/O and memory without CPU intervention. The DMA controller (e.g., 8257/8237) takes bus control via HOLD/HLDA, transfers data using address and count registers, and signals terminal count when done. It enables high-speed bulk transfers.

## Answer

**Direct Memory Access (DMA)** is a technique in which data is transferred directly between an I/O device and memory without the microprocessor handling each byte. A **DMA controller** (Intel **8257** or **8237**) takes control of the system buses for the transfer. It is used for fast, bulk transfers such as disk and display data, where program-controlled or interrupt-driven I/O would be too slow.

**Basic operation**
1. The device raises **DREQ** (DMA request) to the controller.
2. The controller sends **HOLD** to the CPU.
3. The CPU finishes its current machine cycle, floats its buses and replies **HLDA** (hold acknowledge).
4. The controller sends **DACK** to the device, places the memory address on the address bus and issues MEMR/MEMW and IOR/IOW signals; data moves directly.
5. The address register is incremented and the count register decremented; when the count reaches zero, the terminal count (TC) signal ends the transfer and the controller releases HOLD. The CPU resumes.

```text
 I/O device <--DREQ/DACK--> DMA controller --HOLD--> CPU
                                  <--HLDA-----------
            data bus <-------> Memory (address by DMAC)
```

**Features of 8257:** 4 independent channels, each with a 16-bit address register and 14-bit terminal count register; priority fixed or rotating; modes: read, write, verify.

**Transfer types:** single-byte (cycle stealing), block (burst) and demand transfer.

**Advantages:** high speed, CPU is free for other work. **Drawback:** extra hardware, and the CPU is held off the bus during the transfer.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. After an I/O device raises DREQ, what does the DMA controller do next?
   A. Sends DACK to the device immediately
   B. Sends HOLD to the CPU and waits for HLDA
   C. Interrupts the CPU through the INTR pin
   D. Increments the address register and starts the transfer
   Answer: B. The controller must first get the buses: it sends HOLD and only after the CPU replies HLDA does it send DACK and begin the transfer. (Key point: DMA request sequence)

2. What ends a DMA transfer and returns control to the CPU?
   A. The CPU sends HLDA again
   B. The address register overflows
   C. The count register reaches zero and TC is issued, so HOLD is released
   D. The device removes DREQ for one clock
   Answer: C. The address register is incremented and the count register decremented for each byte; when count reaches zero, terminal count (TC) ends the transfer and HOLD is released. (Key point: End of transfer)

3. Why is DMA used for fast bulk transfers such as disk data?
   A. Data moves directly between device and memory without the CPU handling each byte, leaving the CPU free
   B. The CPU executes the transfer using faster instructions
   C. DMA removes the need for a memory chip
   D. DMA converts the data to serial form so it moves faster
   Answer: A. The DMA controller takes over the buses and moves data directly, which is much faster than program-controlled or interrupt-driven I/O and frees the CPU. (Key point: Why use DMA)

## Related in other subjects

- [DMA controller block diagram and transfer](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Adma-controller) — Computer Organization and Architecture, chapter 7, asked 6×
- [DMA controller and flow of actions](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Adma-controller-flow) — Embedded System, chapter 5, asked 3×
- [Device controller vs kernel; DMA](https://www.bctengineer.com/question.md?key=semester_6%2Foperating_system%3Adevice-controller-vs-kernel-dma) — Operating System, chapter 6