---
title: "Short note: Programmable Interrupt Controller"
subject: "Microprocessor"
chapter: 5
key: "semester_4/microprocessor:short-note-pic"
source: https://www.bctengineer.com/q/semester_4/microprocessor/short-note-pic
site: BCT Engineering
---

# Short note: Programmable Interrupt Controller

Microprocessor · Chapter 5: Interrupt Operations

- Asked in: 2069 Bhadra, 4 marks
- Video: [Programmable Interrupt Controller 8259A (Basics, Features, Block Diagram, Working & Operation)](https://www.youtube.com/watch?v=FgkdNCuySDI) — Engineering Funda
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_4/microprocessor/short-note-pic
- Whole chapter: https://www.bctengineer.com/md/semester_4/microprocessor/chapter-5

## Question

Write a short note on Programmable interrupt controller (PIC).

## Short answer

A PIC like Intel 8259A manages up to 8 interrupts (64 by cascading), resolves priority, and masks individual inputs. It sends INT to the CPU and supplies the type number on the data bus during INTA cycles. It is programmed via ICWs and OCWs.

## Answer

A **Programmable Interrupt Controller (PIC)** is a support chip that manages interrupt requests from several I/O devices and presents them to the processor through its single interrupt input. The standard chip for 8085 and 8086 systems is the Intel **8259A**.

#### Main features of the 8259A

- Handles 8 interrupt requests (IR0–IR7); up to 64 using one master and 8 slaves (cascading).
- Resolves priority: fixed priority, rotating priority, or special mask mode, programmable by software.
- Each input can be masked individually.
- For the 8086 it supplies the 8-bit interrupt type number on the data bus; for the 8085 it supplies a 3-byte CALL instruction (CDH followed by the ISR address).
- Edge-triggered or level-triggered inputs.
- Programmed with initialisation command words (ICW1–ICW4) and operation command words (OCW1–OCW3).

#### Internal blocks

```text
 IR0..IR7 --> [IRR] -> [Priority] -> [ISR]
                |        resolver      |
              [IMR]                     v
                                  Control logic -> INT
 INTA' ---> Control logic        D7-D0 <-> data buffer
 CS', RD', WR', A0 -> read/write logic
 CAS0-2, SP/EN -> cascade buffer
```

- **IRR:** holds the pending requests. **IMR:** holds the mask bits. **ISR:** shows the request in service.
- **Priority resolver:** selects the highest-priority request.

#### Working (8086)

A device raises IRn. The 8259A sets the IRR bit and, if the request is unmasked and has the highest priority, sends INT to the CPU. When the CPU replies with INTA' pulses, the 8259A places the type number on the data bus and sets the ISR bit. The ISR ends with an EOI command.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. What is the purpose of a PIC such as the 8259A?
   A. To manage requests from several devices and present them through one interrupt input
   B. To store the interrupt vectors
   C. To disable all interrupts
   D. To perform arithmetic in the ALU
   Answer: A. The PIC handles multiple devices, priority and masks, sending a single INT to the CPU. (Key point: Purpose)

2. Which register in the 8259A holds the pending requests?
   A. IRR
   B. IMR
   C. ISR
   D. OCW
   Answer: A. IRR holds pending requests, IMR holds masks and ISR shows the request in service. (Key point: Internal registers)

3. How many interrupt requests can one 8259A handle, and how can this be extended?
   A. 4, up to 16 by cascading
   B. 16, up to 256 by cascading
   C. 8, up to 64 by cascading one master and 8 slaves
   D. 8, but it cannot be extended
   Answer: C. IR0-IR7 give 8 inputs, and master-slave cascading gives 64. (Key point: Capacity)