---
title: "Six stage pipeline technique"
subject: "Microprocessor"
chapter: 6
key: "semester_4/microprocessor:six-stage-pipeline"
source: https://www.bctengineer.com/q/semester_4/microprocessor/six-stage-pipeline
site: BCT Engineering
---

# Six stage pipeline technique

Microprocessor · Chapter 6: Advanced Topics

- Asked in: 2075 Baisakh, 4 marks
- Video: [Pipelining In Computer Organization Architecture](https://www.youtube.com/watch?v=zF23S5PcUT8) — Sudhakar Atchala
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_4/microprocessor/six-stage-pipeline
- Whole chapter: https://www.bctengineer.com/md/semester_4/microprocessor/chapter-6

## Question

Explain six stage pipeline technique with an example.

## Short answer

Six stages are FI, DI, CO, FO, EI, WO. Overlapping four instructions takes 9 cycles instead of 24; after filling, one instruction completes per cycle. Speed-up = nk/(k+n−1), approaching 6.

## Answer

Pipelining overlaps the execution of several instructions by dividing instruction processing into stages. Each stage works on a different instruction in each clock cycle, like stations of an assembly line.

#### The six stages

1. **FI – Fetch Instruction:** read the instruction from memory.
2. **DI – Decode Instruction:** find the opcode and operand specifiers.
3. **CO – Calculate Operands:** compute the effective address of each operand.
4. **FO – Fetch Operands:** read the operands from memory or registers.
5. **EI – Execute Instruction:** perform the operation.
6. **WO – Write Operand:** store the result.

#### Example: 4 instructions, one clock per stage

```text
Time    1  2  3  4  5  6  7  8  9
I1     FI DI CO FO EI WO         
I2        FI DI CO FO EI WO      
I3           FI DI CO FO EI WO   
I4              FI DI CO FO EI WO
```

- Without pipelining, 4 instructions take 4 × 6 = 24 clock cycles.
- With the six-stage pipeline: k + (n − 1) = 6 + 3 = **9 cycles**.
- After the pipeline is full (cycle 6), one instruction completes in each cycle.
- For n = 9 instructions: 54 cycles without pipeline; 6 + 8 = 14 cycles with it, speed-up = 54/14 ≈ 3.86.

Speed-up = n·k / (k + n − 1), which approaches k = 6 for a large number of instructions.

Pipeline hazards (resource conflicts, data dependence, branches) can stall the pipeline and reduce the speed-up.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. Which is the correct order of the six pipeline stages?
   A. FI, DI, CO, FO, EI, WO
   B. FI, CO, DI, FO, WO, EI
   C. DI, FI, CO, FO, EI, WO
   D. FI, DI, FO, CO, EI, WO
   Answer: A. Fetch, decode, calculate operands, fetch operands, execute, write operand. (Key point: Stages)

2. How many cycles do 4 instructions take in the 6-stage pipeline?
   A. 24
   B. 9
   C. 10
   D. 6
   Answer: B. k + (n - 1) = 6 + 3 = 9; without pipelining it is 24. (Key point: Cycle count)

3. What does the speed-up n*k/(k+n-1) approach for a very large n?
   A. k, the number of stages (6)
   B. 1
   C. n
   D. k + n
   Answer: A. As n becomes large, n*k/(k+n-1) approaches k. (Key point: Speed-up)

4. What can reduce the pipeline's speed-up?
   A. Hazards such as resource conflicts, data dependence and branches
   B. Using more stages only
   C. Single-cycle instructions
   D. Using a clock
   Answer: A. Hazards stall the pipeline. (Key point: Hazards)

## Related in other subjects

- [Six-stage instruction pipeline](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Asix-stage-pipeline) — Computer Organization and Architecture, chapter 4
- [Pipelining and multi-stage pipeline](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Apipelining-stages) — Embedded System, chapter 2, asked 3×
- [Four-segment instruction pipeline and space-time diagram](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Afour-segment-pipeline) — Computer Organization and Architecture, chapter 4, asked 5×
- [Six-speed machine tool gearbox design](https://www.bctengineer.com/question.md?key=semester_7%2Fmachine_design_ii%3Amachine-tool-speed-ladder-gear) — Machine Design II, chapter 5