---
title: "Synchronous/asynchronous bus; LXI timing"
subject: "Microprocessor"
chapter: 2
key: "semester_4/microprocessor:sync-async-bus-lxi-timing"
source: https://www.bctengineer.com/q/semester_4/microprocessor/sync-async-bus-lxi-timing
site: BCT Engineering
---

# Synchronous/asynchronous bus; LXI timing

Microprocessor · Chapter 2: Programming with 8085 Microprocessor

- Asked in: 2069 Bhadra, 3+5 marks; 2068 Bhadra, 2+6 marks (asked 2 times)
- Video: [How to draw Timing Diagram for any instruction in microprocessor 8085](https://www.youtube.com/watch?v=IAtdp43Z1WI) — Jay Explains
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_4/microprocessor/sync-async-bus-lxi-timing
- Whole chapter: https://www.bctengineer.com/md/semester_4/microprocessor/chapter-2

## Question

Define synchronous and asynchronous bus. Draw and explain the timing diagram of LXI B, 1234H.

## Short answer

A synchronous bus uses a common clock for fixed-timing transfers; an asynchronous bus uses handshaking. LXI B,1234H is a 3-byte instruction taking 10 T-states: opcode fetch (4T), two memory reads (3T each) to load 34H into C and 12H into B from consecutive addresses.

## Answer

#### Synchronous bus
In a **synchronous bus** all data transfers are controlled by a common clock. Transfers start and end at fixed clock edges, and the timing of each operation is known in advance. It is simple and fast but all devices must work at the same speed; slow devices need wait states. The 8085 bus is synchronous (the READY signal can add wait states).

#### Asynchronous bus
In an **asynchronous bus** there is no common clock. The transfer uses handshaking signals (e.g., request/acknowledge or Data Valid/Data Accepted), so a sender and a receiver of any speed can communicate. It is more flexible but slower and needs more control logic.

| Point | Synchronous | Asynchronous |
|---|---|---|
| Timing | Common clock | Handshake signals |
| Speed of devices | Same | Any |
| Complexity | Simple | Complex |

#### Timing diagram of LXI B,1234H
`LXI B,1234H` loads B = 12H, C = 34H. It is a 3-byte instruction (opcode 01H) with 3 machine cycles: opcode fetch (4T), memory read (3T), memory read (3T) = **10 T-states**. Assume it is stored at 2000H, 2001H, 2002H (bytes 01, 34, 12).

| M-cycle | T | A15-A8 | AD7-AD0 | ALE | Control | IO/M S1 S0 |
|---|---|---|---|---|---|---|
| **M1 (opcode fetch, 4T)** | T1 | 20H | 00H (PCL) | 1 | - | 0 1 1 |
|  | T2 | 20H | Hi-Z (bus floats) | 0 | RD low | 0 1 1 |
|  | T3 | 20H | 01H (opcode in) | 0 | RD low, rises at end | 0 1 1 |
|  | T4 | - | - | 0 | none (decode) | 0 1 1 |
| **M2 (memory read, 3T)** | T1 | 20H | 01H | 1 | - | 0 1 0 |
|  | T2 | 20H | Hi-Z (bus floats) | 0 | RD low | 0 1 0 |
|  | T3 | 20H | 34H (data in) | 0 | RD low, rises at end | 0 1 0 |
| **M3 (memory read, 3T)** | T1 | 20H | 02H | 1 | - | 0 1 0 |
|  | T2 | 20H | Hi-Z (bus floats) | 0 | RD low | 0 1 0 |
|  | T3 | 20H | 12H (data in) | 0 | RD low, rises at end | 0 1 0 |

```text
      |   M1 (OF)   |  M2 (MR)  |  M3 (MR)  |
      |T1 |T2 |T3 |T4 |T1 |T2 |T3 |T1 |T2 |T3 |
 ALE  |HI |lo |lo |lo |HI |lo |lo |HI |lo |lo |
 RD   |hi |LO |LO |hi |hi |LO |LO |hi |LO |LO |
 WR   |hi |hi |hi |hi |hi |hi |hi |hi |hi |hi |
 (HI/hi = high level, LO/lo = low level)
```

#### Explanation
1. **M1**: In T1 the address 2000H (PC) is put on the bus: 20H on A15-A8 and 00H on AD7-AD0, with ALE = 1 so an external latch holds the low byte. IO/M = 0, S1 = S0 = 1. In T2 RD goes low and the memory puts the opcode 01H on the data bus; the CPU reads it in T3 and stores it in IR. T4 is used to decode it; PC = 2001H.
2. **M2**: Address 2001H is sent in T1 (ALE = 1). RD is low during T2-T3 and the byte 34H is read into register C. PC = 2002H.
3. **M3**: Address 2002H is sent, RD low, byte 12H is read into register B. PC = 2003H.

Total = 4 + 3 + 3 = 10 T-states.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. The 8085 bus is synchronous. How does a slow memory get enough time to respond?
   A. It sends an acknowledge signal and the CPU waits for it, like on an asynchronous bus
   B. It pulls READY low so the CPU inserts wait states
   C. The CPU automatically lowers its clock frequency
   D. It cannot; on a synchronous bus all devices must already be fast enough
   Answer: B. On a synchronous bus all transfers follow a common clock, so a slow device needs wait states. In the 8085 these are added when READY is low. (Key point: Synchronous bus uses a common clock; slow devices need wait states (READY))

2. Which statement correctly describes an asynchronous bus?
   A. All transfers start and end at fixed clock edges known in advance
   B. It is simpler and faster than a synchronous bus
   C. All devices on it must work at the same speed
   D. There is no common clock; handshake signals such as request/acknowledge control the transfer
   Answer: D. An asynchronous bus uses handshaking instead of a shared clock, so devices of any speed can talk. It is more flexible but slower and needs more control logic. (Key point: Asynchronous bus uses handshake signals instead of a common clock)

3. What machine cycles does LXI B,1234H have, and how many T-states in total?
   A. Opcode fetch (4T) + memory read (3T) + memory read (3T) = 10 T-states
   B. Opcode fetch (4T) + memory read (3T) = 7 T-states
   C. Opcode fetch (4T) + memory read (3T) + memory write (3T) = 10 T-states
   D. Opcode fetch (4T) + memory read (3T) + memory read (3T) + memory write (3T) = 13 T-states
   Answer: A. LXI is a 3-byte instruction: one opcode fetch and two memory reads for the 16-bit data. Nothing is written to memory, so the total is 4 + 3 + 3 = 10 T-states. (Key point: LXI B,1234H = OF(4T) + MR(3T) + MR(3T) = 10 T-states)

4. LXI B,1234H is stored at 2000H. In machine cycle M2 (address 2001H), which byte is read and where does it go?
   A. 12H, into register B
   B. 34H, into register B
   C. 34H, into register C
   D. 12H, into register C
   Answer: C. The data is stored low byte first, so 2001H holds 34H, which goes to C. In M3, 12H is read from 2002H into B. (Key point: Low data byte (34H) is read first in M2 into C; high byte 12H into B in M3)

## Related in Microprocessor

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- [Synchronous vs asynchronous serial transmission](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Async-async-serial) — Microprocessor, chapter 4, asked 3×
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