---
title: "Execution of ANI 4BH with timing"
subject: "Microprocessor"
chapter: 2
key: "semester_4/microprocessor:timing-ani-4bh"
source: https://www.bctengineer.com/q/semester_4/microprocessor/timing-ani-4bh
site: BCT Engineering
---

# Execution of ANI 4BH with timing

Microprocessor · Chapter 2: Programming with 8085 Microprocessor

- Asked in: 2075 Baisakh, 5 marks
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_4/microprocessor/timing-ani-4bh
- Whole chapter: https://www.bctengineer.com/md/semester_4/microprocessor/chapter-2

## Question

Explain the execution of instruction ANI 4BH in 8085 with the help of timing diagram.

## Short answer

ANI 4BH ANDs accumulator with immediate byte 4BH, result in A. It sets AC=1, CY=0, and S, Z, P per result. The 2-byte instruction has opcode fetch (4T) and memory read (3T), total 7 T-states.

## Answer

`ANI 4BH` (opcode E6H) ANDs the accumulator with the immediate byte 4BH and stores the result in A: A <- A AND 4BH. It sets AC = 1, clears CY, and sets S, Z, P by the result. It is a 2-byte instruction with 2 machine cycles: opcode fetch (4T) and memory read (3T) = **7 T-states**. Assume it is stored at 2000H, 2001H.

| M-cycle | T | A15-A8 | AD7-AD0 | ALE | Control | IO/M S1 S0 |
|---|---|---|---|---|---|---|
| **M1 (opcode fetch, 4T)** | T1 | 20H | 00H (PCL) | 1 | - | 0 1 1 |
|  | T2 | 20H | Hi-Z (bus floats) | 0 | RD low | 0 1 1 |
|  | T3 | 20H | E6H (opcode in) | 0 | RD low, rises at end | 0 1 1 |
|  | T4 | - | - | 0 | none (decode) | 0 1 1 |
| **M2 (memory read, 3T)** | T1 | 20H | 01H | 1 | - | 0 1 0 |
|  | T2 | 20H | Hi-Z (bus floats) | 0 | RD low | 0 1 0 |
|  | T3 | 20H | 4BH (data in) | 0 | RD low, rises at end | 0 1 0 |

```text
      |  M1 (OF)  | M2 (MR) |
      |T1 T2 T3 T4|T1 T2 T3 |
 ALE  |HI lo lo lo|HI lo lo |
 RD   |hi LO LO hi|hi LO LO |
 WR   |hi hi hi hi|hi hi hi |
```

#### Explanation
1. **M1**: PC = 2000H on the bus with ALE = 1 in T1. RD low in T2-T3; opcode E6H is read into IR. In T4 it is decoded and the CPU knows one more byte is needed.
2. **M2**: PC = 2001H on the bus; RD low; the data byte 4BH is read into a temporary register. At the end of this cycle the ALU performs A AND 4BH and the result goes back to A.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. How many machine cycles and T-states does ANI 4BH take?
   A. 1 machine cycle (opcode fetch), 4 T-states
   B. 3 machine cycles, 10 T-states
   C. 2 machine cycles (opcode fetch + memory read), 7 T-states
   D. 2 machine cycles (opcode fetch + memory write), 7 T-states
   Answer: C. ANI is a 2-byte instruction. It fetches the opcode E6H (4T) and then reads the immediate byte 4BH in a memory read (3T), for a total of 7T. (Key point: ANI 4BH: 2 bytes, 2 machine cycles (OF + MR), 7 T-states)

2. Which flag effect does ANI 4BH have?
   A. AC = 1, CY = 0, and S, Z, P are set by the result
   B. AC = 0, CY = 0, and S, Z, P are set by the result
   C. CY is set if the result is negative
   D. No flags are affected, as with MOV
   Answer: A. AND operations in the 8085 always set AC and reset CY. S, Z and P depend on A AND 4BH. (Key point: ANI sets AC = 1 and clears CY; S, Z, P follow the result)

3. What happens in the second machine cycle of ANI 4BH (stored at 2000H-2001H)?
   A. The result of A AND 4BH is written to memory location 2001H
   B. 4BH is read from 2001H into a temporary register, then A AND 4BH goes to A
   C. Nothing new is read; the AND was already done in T4 of M1
   D. The operand is read from the memory location whose address is 4BH
   Answer: B. In M2, PC = 2001H is placed on the bus and RD goes low, so the immediate byte 4BH is read into a temporary register. The AND is done at the end of this cycle, and the result goes back to A, not to memory. (Key point: In M2, 4BH is read and then the ALU ANDs it with A)

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