---
title: "Execution of LDA 8B7FH with timing"
subject: "Microprocessor"
chapter: 2
key: "semester_4/microprocessor:timing-lda-8b7fh"
source: https://www.bctengineer.com/q/semester_4/microprocessor/timing-lda-8b7fh
site: BCT Engineering
---

# Execution of LDA 8B7FH with timing

Microprocessor · Chapter 2: Programming with 8085 Microprocessor

- Asked in: 2070 Bhadra, 8 marks
- Video: [Timing Diagram of LDA Instruction in 8085 Microprocessor  | Timing Diagram](https://www.youtube.com/watch?v=euRRcFmN8nQ) — Engineering Funda
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_4/microprocessor/timing-lda-8b7fh
- Whole chapter: https://www.bctengineer.com/md/semester_4/microprocessor/chapter-2

## Question

Explain the execution of instruction LDA 8B7FH with the help of timing diagram.

## Short answer

LDA 8B7FH (opcode 3AH) loads A from address 8B7FH. It uses four cycles: opcode fetch, two reads to form address (7FH, 8BH), and a data read, totaling 13 T-states.

## Answer

`LDA 8B7FH` (opcode 3AH) copies the byte stored at memory location 8B7FH into the accumulator. It is a 3-byte instruction (3AH, 7FH, 8BH) with 4 machine cycles and 13 T-states. Assume it is stored at 2000H.

#### Execution step by step
1. **M1, opcode fetch (T1-T4)**: PC = 2000H appears on the address bus (20H on A15-A8, 00H on AD7-AD0); ALE = 1 in T1 so that the low byte is latched. IO/M = 0, S1 = S0 = 1. RD goes low in T2; the memory returns 3AH, read by the CPU into the instruction register at T3. T4 decodes the opcode. PC = 2001H.
2. **M2, memory read (T1-T3)**: address 2001H; RD low in T2-T3; byte 7FH (low order address) is stored in register Z. PC = 2002H.
3. **M3, memory read (T1-T3)**: address 2002H; byte 8BH (high order address) is stored in W. PC = 2003H.
4. **M4, memory read (T1-T3)**: address WZ = 8B7FH; 8BH on A15-A8 and 7FH on AD7-AD0 with ALE high in T1. RD is low during T2-T3 and the data byte from 8B7FH is read into A.

| M-cycle | T | A15-A8 | AD7-AD0 | ALE | Control | IO/M S1 S0 |
|---|---|---|---|---|---|---|
| **M1 (opcode fetch, 4T)** | T1 | 20H | 00H (PCL) | 1 | - | 0 1 1 |
|  | T2 | 20H | Hi-Z (bus floats) | 0 | RD low | 0 1 1 |
|  | T3 | 20H | 3AH (opcode in) | 0 | RD low, rises at end | 0 1 1 |
|  | T4 | - | - | 0 | none (decode) | 0 1 1 |
| **M2 (memory read, 3T)** | T1 | 20H | 01H | 1 | - | 0 1 0 |
|  | T2 | 20H | Hi-Z (bus floats) | 0 | RD low | 0 1 0 |
|  | T3 | 20H | 7FH (data in) | 0 | RD low, rises at end | 0 1 0 |
| **M3 (memory read, 3T)** | T1 | 20H | 02H | 1 | - | 0 1 0 |
|  | T2 | 20H | Hi-Z (bus floats) | 0 | RD low | 0 1 0 |
|  | T3 | 20H | 8BH (data in) | 0 | RD low, rises at end | 0 1 0 |
| **M4 (memory read, 3T)** | T1 | 8BH | 7FH | 1 | - | 0 1 0 |
|  | T2 | 8BH | Hi-Z (bus floats) | 0 | RD low | 0 1 0 |
|  | T3 | 8BH | data (data in) | 0 | RD low, rises at end | 0 1 0 |

```text
 Status: M1 = (IO/M,S1,S0) 0 1 1 ; M2,M3,M4 = 0 1 0
 Total T-states = 4 + 3 + 3 + 3 = 13
```

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. How many machine cycles and T-states does LDA 8B7FH take?
   A. 3 machine cycles, 10 T-states
   B. 4 machine cycles, 13 T-states
   C. 4 machine cycles, 16 T-states
   D. 3 machine cycles, 13 T-states
   Answer: B. LDA needs opcode fetch (4T) plus three memory reads (3T each): two for the address bytes and one for the data, giving 4 + 3 + 3 + 3 = 13 T-states. (Key point: LDA: 3 bytes, 4 machine cycles, 13 T-states)

2. In M2 and M3 of LDA 8B7FH, which bytes are read and where are they held?
   A. M2 reads 8BH into W, M3 reads 7FH into Z
   B. M2 reads 7FH into the accumulator, M3 reads 8BH into the accumulator
   C. M2 reads 7FH (low address) into Z, M3 reads 8BH (high address) into W
   D. M2 reads 7FH into L, M3 reads 8BH into H
   Answer: C. The instruction is stored as 3A 7F 8B, so M2 reads the low address byte 7FH into Z and M3 reads the high byte 8BH into W. WZ = 8B7FH is then used as the address in M4. (Key point: Address bytes are read low first (7FH to Z), then high (8BH to W))

3. During T1 of M4, what appears on A15-A8 and AD7-AD0?
   A. 20H on A15-A8 and 03H on AD7-AD0 (the next PC value)
   B. 8BH on A15-A8 and 7FH on AD7-AD0, with ALE high
   C. 7FH on A15-A8 and 8BH on AD7-AD0, with ALE high
   D. 8BH on A15-A8 and the data byte on AD7-AD0, with ALE low
   Answer: B. In M4 the CPU sends the operand address WZ = 8B7FH: 8BH on A15-A8 and 7FH on AD7-AD0, with ALE high in T1 to latch the low byte. The data then comes in on AD7-AD0 in T3. (Key point: M4 puts WZ = 8B7FH on the address bus and reads the data into A)

4. What are IO/M, S1, S0 during M1 and during M2-M4 of LDA 8B7FH?
   A. M1 = 0 1 0; M2-M4 = 0 1 1
   B. M1 = 1 1 1; M2-M4 = 1 1 0
   C. M1 = 0 1 1; M2-M4 = 0 0 1
   D. M1 = 0 1 1; M2-M4 = 0 1 0
   Answer: D. All four cycles access memory, so IO/M = 0. The opcode fetch has S1 S0 = 11 and each memory read has S1 S0 = 10. (Key point: Status: opcode fetch 0 1 1, memory read 0 1 0)

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