---
title: "Timing diagram of LXI D, 2465H"
subject: "Microprocessor"
chapter: 2
key: "semester_4/microprocessor:timing-lxi-d-2465h"
source: https://www.bctengineer.com/q/semester_4/microprocessor/timing-lxi-d-2465h
site: BCT Engineering
---

# Timing diagram of LXI D, 2465H

Microprocessor · Chapter 2: Programming with 8085 Microprocessor

- Asked in: 2073 Magh, 6+2 marks
- Video: [5. Timing diagram 8085 | LXI Instruction](https://www.youtube.com/watch?v=Gz4-2f5ZA-k) — Game Of Codes
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_4/microprocessor/timing-lxi-d-2465h
- Whole chapter: https://www.bctengineer.com/md/semester_4/microprocessor/chapter-2

## Question

Draw and explain the timing diagram of LXI D, 2465H. Calculate the time required to execute this instruction if the crystal frequency is 6 MHz.

## Short answer

LXI D,2465H has three cycles: opcode fetch (11H), read 65H to E, read 24H to D, total 10 T-states. With 6 MHz crystal, T=0.333 µs, time = 10×0.333 = 3.33 µs.

## Answer

`LXI D,2465H` (opcode 11H) loads the register pair DE with 2465H, that is D = 24H and E = 65H. It is a 3-byte instruction (11H, 65H, 24H) with three machine cycles: opcode fetch (4T), memory read (3T), memory read (3T) = **10 T-states**. Assume it is stored at 2000H.

| M-cycle | T | A15-A8 | AD7-AD0 | ALE | Control | IO/M S1 S0 |
|---|---|---|---|---|---|---|
| **M1 (opcode fetch, 4T)** | T1 | 20H | 00H (PCL) | 1 | - | 0 1 1 |
|  | T2 | 20H | Hi-Z (bus floats) | 0 | RD low | 0 1 1 |
|  | T3 | 20H | 11H (opcode in) | 0 | RD low, rises at end | 0 1 1 |
|  | T4 | - | - | 0 | none (decode) | 0 1 1 |
| **M2 (memory read, 3T)** | T1 | 20H | 01H | 1 | - | 0 1 0 |
|  | T2 | 20H | Hi-Z (bus floats) | 0 | RD low | 0 1 0 |
|  | T3 | 20H | 65H (data in) | 0 | RD low, rises at end | 0 1 0 |
| **M3 (memory read, 3T)** | T1 | 20H | 02H | 1 | - | 0 1 0 |
|  | T2 | 20H | Hi-Z (bus floats) | 0 | RD low | 0 1 0 |
|  | T3 | 20H | 24H (data in) | 0 | RD low, rises at end | 0 1 0 |

```text
      |  M1 (OF)  | M2 (MR) | M3 (MR) |
      |T1 T2 T3 T4|T1 T2 T3 |T1 T2 T3 |
 ALE  |HI lo lo lo|HI lo lo |HI lo lo |
 RD   |hi LO LO hi|hi LO LO |hi LO LO |
 WR   |hi hi hi hi|hi hi hi |hi hi hi |
```

#### Explanation
- **M1**: opcode 11H is fetched from 2000H and decoded in T4.
- **M2**: address 2001H; data byte 65H is read and stored in E (low-order register of the pair).
- **M3**: address 2002H; data byte 24H is read and stored in D.

No write operation takes place, so WR stays high throughout.

#### Time
Crystal = 6 MHz, so the internal clock = 6 / 2 = 3 MHz and T = 0.333 microsecond.

Time = 10 x 0.333 = **3.33 microseconds**.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. LXI D,2465H is stored at 2000H. What byte is read in M2 and where does it go?
   A. 24H, into D
   B. 11H, into the instruction register
   C. 24H, into E
   D. 65H, into E
   Answer: D. The instruction bytes are 11H, 65H, 24H (low data byte first). M2 reads 65H from 2001H into E, the low-order register of the pair. (Key point: Low byte 65H read first (M2) into E; 24H into D)

2. With a 6 MHz crystal, how long does LXI D,2465H (10 T-states) take?
   A. 1.67 microseconds
   B. 3.33 microseconds
   C. 6.67 microseconds
   D. 0.6 microseconds
   Answer: B. The 8085 divides the crystal frequency by 2, so the clock is 3 MHz and T = 0.333 microsecond. 10 x 0.333 = 3.33 microseconds. (Key point: Internal clock = crystal / 2: 6 MHz gives T = 0.333 us, 10T = 3.33 us)

3. In T1 of M3 (instruction stored at 2000H), what is on AD7-AD0?
   A. 24H, the data byte
   B. Hi-Z, the bus floats
   C. 02H, the low byte of address 2002H
   D. 00H, the low byte of the opcode address
   Answer: C. M3 reads from 2002H. In T1, ALE is high and AD7-AD0 carries the low address byte 02H; the data 24H comes later, in T3. (Key point: In T1 of each read cycle AD7-AD0 carries the low address byte)

4. What happens in T4 of the opcode fetch cycle of LXI D,2465H?
   A. The opcode 11H is decoded; no RD or WR is active
   B. The first data byte 65H is read from memory
   C. WR goes low to store DE in memory
   D. ALE goes high again to latch the next address
   Answer: A. The opcode is read into IR in T3, and T4 is used to decode it. RD and WR stay high, and the data bytes are read in M2 and M3. (Key point: T4 of the opcode fetch is used to decode the opcode)

## Close variants set in other exams

- [Timing diagram of LDA 2080H](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Atiming-lda-2080h) — Microprocessor, chapter 2, asked 2×

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