--- title: "Bus timing of OUT 42H" subject: "Microprocessor" chapter: 2 key: "semester_4/microprocessor:timing-out-42h" source: https://www.bctengineer.com/q/semester_4/microprocessor/timing-out-42h site: BCT Engineering --- # Bus timing of OUT 42H Microprocessor · Chapter 2: Programming with 8085 Microprocessor - Asked in: 2071 Bhadra, 8 marks - Video: [Timing Diagram of OUT Instruction in 8085 Microprocessor | Timing Diagram](https://www.youtube.com/watch?v=YDJ8wucEyig) — Engineering Funda - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_4/microprocessor/timing-out-42h - Whole chapter: https://www.bctengineer.com/md/semester_4/microprocessor/chapter-2 ## Question Draw and explain the bus timing for OUT 42H instruction of 8085 microprocessor. ## Short answer OUT 42H outputs accumulator to port 42H. It has opcode fetch (4T), memory read of the port address (3T), and I/O write (3T) = 10 T-states. In I/O write, address 42H appears on A15–A8 and AD7–AD0, WR goes low, and accumulator data is sent. ## Answer `OUT 42H` (opcode D3H) sends the content of the accumulator to the output port whose 8-bit address is 42H. It is a 2-byte instruction with 3 machine cycles: opcode fetch (4T), memory read (3T), I/O write (3T) = **10 T-states**. Assume it is stored at 2000H, 2001H. | M-cycle | T | A15-A8 | AD7-AD0 | ALE | Control | IO/M S1 S0 | |---|---|---|---|---|---|---| | **M1 (opcode fetch, 4T)** | T1 | 20H | 00H (PCL) | 1 | - | 0 1 1 | | | T2 | 20H | Hi-Z (bus floats) | 0 | RD low | 0 1 1 | | | T3 | 20H | D3H (opcode in) | 0 | RD low, rises at end | 0 1 1 | | | T4 | - | - | 0 | none (decode) | 0 1 1 | | **M2 (memory read, 3T)** | T1 | 20H | 01H | 1 | - | 0 1 0 | | | T2 | 20H | Hi-Z (bus floats) | 0 | RD low | 0 1 0 | | | T3 | 20H | 42H (data in) | 0 | RD low, rises at end | 0 1 0 | | **M3 (I/O write, 3T)** | T1 | 42H | 42H | 1 | - | 1 0 1 | | | T2 | 42H | A (data out) | 0 | WR low | 1 0 1 | | | T3 | 42H | A | 0 | WR low, rises at end | 1 0 1 | ```text | M1 (OF) | M2 (MR) | M3 (IOW)| |T1 T2 T3 T4|T1 T2 T3 |T1 T2 T3 | ALE |HI lo lo lo|HI lo lo |HI lo lo | RD |hi LO LO hi|hi LO LO |hi hi hi | WR |hi hi hi hi|hi hi hi |hi LO LO | IO/M |lo lo lo lo|lo lo lo |HI HI HI | ``` #### Explanation 1. **M1 (opcode fetch)**: address 2000H on the bus, ALE = 1 in T1, IO/M = 0, S1 = S0 = 1. RD goes low in T2-T3 and D3H is read into IR; decoded in T4. 2. **M2 (memory read)**: address 2001H; RD low; the port address 42H is read into registers W and Z. 3. **M3 (I/O write)**: IO/M goes high (I/O operation), S1 = 0, S0 = 1. The 8-bit port address 42H is placed on both A15-A8 and AD7-AD0 in T1 (ALE = 1). In T2 the content of A is put on AD7-AD0 and WR goes low; the port latches the data when WR goes high at the end of T3. Total = 4 + 3 + 3 = 10 T-states. Memory is not accessed in the third cycle because IO/M = 1. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What machine cycles make up OUT 42H, and how many T-states in total? A. Opcode fetch, memory read, I/O write: 4 + 3 + 3 = 10 T-states B. Opcode fetch, I/O write: 4 + 3 = 7 T-states C. Opcode fetch, memory read, memory write: 4 + 3 + 3 = 10 T-states D. Opcode fetch, memory read, memory read, I/O write: 13 T-states Answer: A. OUT 42H is 2 bytes: the opcode fetch (4T) reads D3H, a memory read (3T) gets the port address 42H, and an I/O write (3T) sends A to the port, giving 10 T-states. (Key point: OUT: opcode fetch + memory read + I/O write = 10 T-states) 2. In T1 of the I/O write cycle (M3) of OUT 42H, what is on the address lines? A. 00H on A15-A8 and 42H on AD7-AD0 B. 20H on A15-A8 and 02H on AD7-AD0 (the next PC value) C. 42H on both A15-A8 and AD7-AD0 D. 42H on A15-A8 and the accumulator content on AD7-AD0 Answer: C. A port address is only 8 bits, so the 8085 places 42H on both the high-order lines and the low-order AD7-AD0 lines in T1, with ALE high. (Key point: In the I/O write cycle the 8-bit port address appears on both A15-A8 and AD7-AD0) 3. What are the control and status signals during M3 of OUT 42H? A. IO/M = 0, S1 = 0, S0 = 1, WR low B. IO/M = 1, S1 = 1, S0 = 0, RD low C. IO/M = 1, S1 = 1, S0 = 1, WR low D. IO/M = 1, S1 = 0, S0 = 1, WR low Answer: D. M3 is an I/O operation, so IO/M = 1, and it is a write, so S1 S0 = 01 and WR goes low. Because IO/M = 1, memory is not accessed in this cycle. (Key point: I/O write status: IO/M = 1, S1 = 0, S0 = 1 and WR low) 4. When does the output port receive the accumulator content during OUT 42H? A. In T1 of M3, together with the port address B. A is put on AD7-AD0 in T2 of M3 with WR low, and the port latches it when WR goes high at the end of T3 C. In T4 of M1, while the opcode is decoded D. In T3 of M2, when 42H is read from memory Answer: B. After the port address is sent in T1, the CPU places A on AD7-AD0 in T2 and drives WR low. The port latches the data on the rising edge of WR at the end of T3. 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